[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v1 7/7] x86/vmx: switch IPT MSRs on vmentry/vmexit
Enable IPT when entering the VM and disable it on vmexit. Register state is persisted using vCPU ipt_state structure. Signed-off-by: Michal Leszczynski <michal.leszczynski@xxxxxxx> --- xen/arch/x86/hvm/vmx/vmx.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 97104c319e..01d9a7b584 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3698,6 +3698,15 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) __vmread(GUEST_RSP, ®s->rsp); __vmread(GUEST_RFLAGS, ®s->rflags); + if ( unlikely(v->arch.hvm.vmx.ipt_state) ) + { + wrmsrl(MSR_IA32_RTIT_CTL, 0); + smp_rmb(); + + rdmsrl(MSR_IA32_RTIT_STATUS, v->arch.hvm.vmx.ipt_state->status); + rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, v->arch.hvm.vmx.ipt_state->output_mask); + } + hvm_invalidate_regs_fields(regs); if ( paging_mode_hap(v->domain) ) @@ -4497,6 +4506,23 @@ bool vmx_vmenter_helper(const struct cpu_user_regs *regs) } out: + if ( unlikely(curr->arch.hvm.vmx.ipt_state) ) + { + wrmsrl(MSR_IA32_RTIT_CTL, 0); + + if (curr->arch.hvm.vmx.ipt_state->ctl) + { + wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, curr->arch.hvm.vmx.ipt_state->output_base); + wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, curr->arch.hvm.vmx.ipt_state->output_mask); + wrmsrl(MSR_IA32_RTIT_STATUS, curr->arch.hvm.vmx.ipt_state->status); + + // MSR_IA32_RTIT_CTL is context-switched manually instead of being + // stored inside VMCS, as of Q2'20 only the most recent processors + // support such field in VMCS + wrmsrl(MSR_IA32_RTIT_CTL, curr->arch.hvm.vmx.ipt_state->ctl); + } + } + if ( unlikely(curr->arch.hvm.vmx.lbr_flags & LBR_FIXUP_MASK) ) lbr_fixup(); -- 2.20.1
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