[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH] x86/Intel: insert Ice Lake and Comet Lake model numbers
Both match prior generation processors as far as LBR and C-state MSRs go (SDM rev 072) as well as applicability of the if_pschange_mc erratum (recent spec updates). Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> --- Such changes having been subject to backporting in the past, this change may want considering for 4.14. --- I'm leaving alone spec_ctrl.c, albeit there's a scary looking erratum for Ice Lake indicating that MDS_NO may wrongly be set. But this is apparently addressed by ucode update, so we may not need to deal with it in software. --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -180,9 +180,15 @@ static void do_get_hw_residencies(void * case 0x4E: case 0x55: case 0x5E: + /* Ice Lake */ + case 0x7D: + case 0x7E: /* Kaby Lake */ case 0x8E: case 0x9E: + /* Comet Lake */ + case 0xA5: + case 0xA6: GET_PC2_RES(hw_res->pc2); GET_CC7_RES(hw_res->cc7); /* fall through */ --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2438,8 +2438,12 @@ static bool __init has_if_pschange_mc(vo case 0x4e: /* Skylake M */ case 0x5e: /* Skylake D */ case 0x55: /* Skylake-X / Cascade Lake */ + case 0x7d: /* Ice Lake */ + case 0x7e: /* Ice Lake */ case 0x8e: /* Kaby / Coffee / Whiskey Lake M */ case 0x9e: /* Kaby / Coffee / Whiskey Lake D */ + case 0xa5: /* Comet Lake H/S */ + case 0xa6: /* Comet Lake U */ return true; /* @@ -2781,10 +2785,14 @@ static const struct lbr_info *last_branc case 0x66: /* Goldmont Plus */ case 0x7a: + /* Ice Lake */ + case 0x7d: case 0x7e: /* Tremont */ case 0x86: /* Kaby Lake */ case 0x8e: case 0x9e: + /* Comet Lake */ + case 0xa5: case 0xa6: return sk_lbr; /* Atom */ case 0x1c: case 0x26: case 0x27: case 0x35: case 0x36:
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