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Re: [Xen-devel] [PATCH v7 1/3] x86/tlb: introduce a flush HVM ASIDs flag

On Thu, Mar 19, 2020 at 06:07:44PM +0000, Julien Grall wrote:
> On 19/03/2020 17:38, Roger Pau Monné wrote:
> > On Thu, Mar 19, 2020 at 04:21:23PM +0000, Julien Grall wrote:
> >  >> Why can't you keep flush_tlb_mask() here?
> > 
> > Because filtered_flush_tlb_mask is used in populate_physmap, and
> > changes to the phymap require an ASID flush on AMD hardware.
> I am afraid this does not yet explain me why flush_tlb_mask() could not be
> updated so it flush the ASID on AMD hardware.

Current behavior previous to this patch is to flush the ASIDs on
every TLB flush.

flush_tlb_mask is too widely used on x86 in places where there's no
need to flush the ASIDs. This prevents using assisted flushes (by L0)
when running nested, since those assisted flushes performed by L0
don't flush the L2 guests TLBs.

I could keep current behavior and leave flush_tlb_mask also flushing the
ASIDs, but that seems wrong as the function doesn't have anything in
it's name that suggests it also flushes the in-guest TLBs for HVM.

I would rather prefer the default to be to not flush the
ASIDs, so that users need to specify so by passing the flag to

> This would actually match the behavior of flush_tlb_mask() on Arm where all
> the guest TLBs would be removed.

That's how it used to be previous to this patch, and the whole point
is to split the ASID flushes into a separate flag, so it's not done
for every TLB flush.

Thanks, Roger.

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