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Re: [Xen-devel] [PATCH] x86/sm{e, a}p: do not enable SMEP/SMAP in PV shim by default on AMD


  • To: Igor Druzhinin <igor.druzhinin@xxxxxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Date: Thu, 16 Jan 2020 16:16:22 +0000
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  • Delivery-date: Thu, 16 Jan 2020 16:16:40 +0000
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  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
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On 16/01/2020 16:00, Igor Druzhinin wrote:
> Due to AMD and Hygon being unable to selectively trap CR4 bit modifications
> running 32-bit PV guest inside PV shim comes with significant performance
> hit. Moreover, for SMEP in particular every time CR4.SMEP changes on context
> switch to/from 32-bit PV guest, it gets trapped by L0 Xen which then
> tries to perform global TLB invalidation for PV shim domain. This usually
> results in eventual hang of a PV shim with at least several vCPUs.
>
> Since the overall security risk is generally lower for shim Xen as it being
> there more of a defense-in-depth mechanism, choose to disable SMEP/SMAP in
> it by default on AMD and Hygon unless a user chose otherwise.
>
> Signed-off-by: Igor Druzhinin <igor.druzhinin@xxxxxxxxxx>
> ---
> I'm a little bit on the fence with this one. We're having the same issue with
> general nested virt but I'm not inclined to trade security for a user in
> general case. Disabling it by default for PV shim only seems rather inocuous
> due to the use case restricion. I'd like to hear more opinions.

So everyone on the list is up to date with the discussion we had IRL.

SMEP/SMAP are defence in depth measures.  We support running on hardware
without these features, and the overall result is the same, security wise.

In the PV Shim case, there is only a single guest and nothing
interesting in Xen, data wise.  We specifically do not have the risk of
sideways data leakage from other guests to be worried about.

We do however care for performance, and not taking a VMExit on every
SYSCALL/Interrupt/Exception makes a massive difference overall.

~Andrew

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