Re: [Xen-devel] HPET interrupt remapping during boot

[Roger Pau Monné <roger.pau@xxxxxxxxxx>]

On Wed, Oct 09, 2019 at 12:41:05PM +0200, Jan Beulich wrote:
> On 09.10.2019 12:11, Roger Pau Monné  wrote:
> > And it does print the following when setting up the iommu:
> > 
> > (XEN) ioapic 0 pin 0 not masked
> > (XEN) vec=00 delivery=ExINT dest=P status=0 polarity=0 irr=0 trig=E mask=0 
> > dest_id:00010000
> > 
> > I wonder, shouldn't all pins of all the io-apics be masked at boot?
> 
> I think you might get different answers here depending on whether
> you ask firmware or OS people. In fact there are cases where the
> IO-APIC needs to be left in this state, I think, but such would
> likely need properly reflecting in ACPI tables (albeit I don't
> know/recall how this would be done; looking at the code ). This goes back to 
> times
> when IO-APICs were new and OSes would not even know about them,
> yet they wouldn't get any interrupts to work if fiddling with
> only the PIC (sitting behind IO-APIC pin 0).
> 
> See enable_IO_APIC(), where we actually use this property to
> determine the pin behind which the 8259 sits.
> 
> I've seen quite many systems where in the BIOS setup you have an
> option to select whether you have an "ACPI OS" (wording of course
> varies). I've never checked whether this may e.g. reflect itself
> in the handover state of the GSI 0 RTE.
> 
> In your testing patch, could you also log the PIC mask bytes?
> There ought to be at least one unmasked; or wait - there actually
> is a spurious interrupt there (right before IOMMU initialization):
> 
> (XEN) spurious 8259A interrupt: IRQ7.

So I've added a log of the PIC masks just before checking the ioapic
masks:

(XEN) 8259A-1 mask: fe 8259A-2 mask: ff

AFAICT IRQ7 seems to be unmasked? Sorry my knowledge of PICs is quite
limited since I've never had to deal with them.

The line I've added is:

printk("8259A-1 mask: %x 8259A-2 mask: %x\n", inb(0x21), inb(0xA1));

I wonder why does Xen even has any code to deal with the PICs,
shouldn't we rely on io-apics only for legacy delivery?

> Hence I wonder if there's not possibly a 2nd one once the IOMMU
> has been set up.

Right, then I guess we either mask all the io-apic pins or we setup
proper remapping entries for non-masked pins? (in order to avoid iommu
faults)

Thanks, Roger.

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