[Xen-devel] [PATCH for-4.13] xen/arm: Implement workaround for Cortex A-57 and Cortex A72 AT speculate

[Julien Grall <julien.grall@xxxxxxx>]

Both Cortex-A57 (erratum 1319537) and Cortex-A72 (erratum 1319367) can
end with corrupt TLBs if they speculate an AT instruction while S1/S2
system registers in inconsistent state.

The workaround is the same as for Cortex A-76 implemented by commit
a18be06aca "xen/arm: Implement workaround for Cortex-A76 erratum 1165522",
so it is only necessary to plumb in the cpuerrata framework.

Signed-off-by: Julien Grall <julien.grall@xxxxxxx>
---
 docs/misc/arm/silicon-errata.txt |  2 ++
 xen/arch/arm/cpuerrata.c         | 10 ++++++++++
 2 files changed, 12 insertions(+)

diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt
index 6cd1366f15..cf193a6d4d 100644
--- a/docs/misc/arm/silicon-errata.txt
+++ b/docs/misc/arm/silicon-errata.txt
@@ -48,5 +48,7 @@ stable hypervisors.
 | ARM            | Cortex-A57      | #852523         | N/A                     
|
 | ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075    
|
 | ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220    
|
+| ARM            | Cortex-A57      | #1319537        | N/A
+| ARM            | Cortex-A72      | #1319367        | N/A
 | ARM            | Cortex-A76      | #1165522        | N/A                     
|
 | ARM            | MMU-500         | #842869         | N/A                     
|
diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
index 6f483b2d8d..da72b02442 100644
--- a/xen/arch/arm/cpuerrata.c
+++ b/xen/arch/arm/cpuerrata.c
@@ -481,6 +481,16 @@ static const struct arm_cpu_capabilities arm_errata[] = {
         .capability = ARM64_WORKAROUND_AT_SPECULATE,
         MIDR_RANGE(MIDR_CORTEX_A76, 0, 2 << MIDR_VARIANT_SHIFT),
     },
+    {
+        .desc = "ARM erratum 1319537",
+        .capability = ARM64_WORKAROUND_AT_SPECULATE,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
+    },
+    {
+        .desc = "ARM erratum 1319367",
+        .capability = ARM64_WORKAROUND_AT_SPECULATE,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
+    },
     {},
 };
 
-- 
2.11.0


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