[Xen-devel] [PATCH v5 00/10] AMD IOMMU: further improvements

[Jan Beulich <jbeulich@xxxxxxxx>]

Only the first patch here is left from v4, everything else is new,
yet still related. The main goal is to reduce the huge memory
overhead that we've noticed. On the way there a number of other
things were once again noticed. Unfortunately before I was able to
also test the last two patches there, my Rome box broke again.
Hence these two patches have been tested on a (less affected)
Fam15 system only.

01: miscellaneous DTE handling adjustments
02: drop stray "else"
03: don't free shared IRT multiple times
04: introduce a "valid" flag for IVRS mappings
05: let callers of amd_iommu_alloc_intremap_table() handle errors
06: don't blindly allocate interrupt remapping tables
07: make phantom functions share interrupt remapping tables
08: x86/PCI: read MSI-X table entry count early
09: replace INTREMAP_ENTRIES
10: restrict interrupt remapping table sizes

Full set of patches once again attached here due to still unresolved
email issues over here.

Jan

Attachment: 01-AMD-IOMMU-misc-DTE.patch
Description: Text document

Attachment: 02-AMD-IOMMU-stray-else.patch
Description: Text document

Attachment: 03-AMD-IOMMU-free-IRTs-shared.patch
Description: Text document

Attachment: 04-AMD-IOMMU-ivrs_mappings-valid.patch
Description: Text document

Attachment: 05-AMD-IOMMU-IRT-alloc-fail.patch
Description: Text document

Attachment: 06-AMD-IOMMU-limit-IRT-allocs.patch
Description: Text document

Attachment: 07-AMD-IOMMU-limit-IRT-phantom-funcs.patch
Description: Text document

Attachment: 08-PCI-read-MSI-X-nr.patch
Description: Text document

Attachment: 09-AMD-IOMMU-replace-INTREMAP_ENTRIES.patch
Description: Text document

Attachment: 10-AMD-IOMMU-limit-IRT-alloc-order.patch
Description: Text document

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