[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Xen-devel] [PATCH 2/2] xen: merge temporary vcpu pinning scenarios
- To: Juergen Gross <JGross@xxxxxxxx>
- From: Jan Beulich <JBeulich@xxxxxxxx>
- Date: Tue, 23 Jul 2019 14:03:21 +0000
- Accept-language: en-US
- Arc-authentication-results: i=1; mx.microsoft.com 1;spf=pass smtp.mailfrom=suse.com;dmarc=pass action=none header.from=suse.com;dkim=pass header.d=suse.com;arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sGKspDcuZ8YNVJBgjd3xckuhB/93Dh4QgtD3KN9/k3g=; b=oCMC6/efE80VMZ22Vlo9bDSYyI00yOGo3Y06wcyWk9k+KCWf3xUUNV0jGGiSxNgwV9yWxX7hVqBabXmFxIHWwWdb1VL/vzyqdlV2SAQGGxbYEoIam6T9n8qs8dHR7zLIl+TV25A/pMIw6JQct1lqMEWxey+W2ViQoHCAQHIVoNvK2QDYEw540xBhHp/D1F08N+6+nmxxThr5RNUkx6EgVM8BdyiejMB6AV/Rhy5X9uMvyGdacp9GaY8BHg20PhH1OMGp0RL9cPDgDoX4gsx0eQ5LpcDfAp0f7rpMtAXrGlkgAN+KvgGi3elKNVESAJkleVK7Ov5ujQVIYTMYoDFezw==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=c1QNwItVZ1xDfuofpjchY/W4Jbyv+UGzPBihUpCDW0Scnor9QmWpzlBGWlcWD37yRJR2IS1+y97lGfhmEok+TDdXtGGpxQmBSVbq9CV0mT9DK5mxp0K6IiWxlzXZfFJuY7pRZe/kRvVYRPZNxT95FXUKGqSlSeyCXbgRBs9bz0IGSHSRCKbXP52Be3jh0gib4lsKrITJYPoo/U8CZ2yX53Kyl7O2SQfgd5/CyWUzKH8KnzRUcBcjYQXjgx+Doz9psdkKj5JgDyHqnznaRvYOlpBDKSGnTGMkjWogjbOHgI2UJylGmqSz21uvywbb2iYwUD/WAPQQD0wrtyY+wYr03A==
- Authentication-results: spf=none (sender IP is ) smtp.mailfrom=JBeulich@xxxxxxxx;
- Cc: Tim Deegan <tim@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>, George Dunlap <George.Dunlap@xxxxxxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Ian Jackson <ian.jackson@xxxxxxxxxxxxx>, Dario Faggioli <dfaggioli@xxxxxxxx>, Julien Grall <julien.grall@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Delivery-date: Tue, 23 Jul 2019 14:05:14 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Thread-index: AQHVQTgCmOXaxQxPLUKxvpzXZTTLrabYJaWAgAARcbKAAAU4gA==
- Thread-topic: [PATCH 2/2] xen: merge temporary vcpu pinning scenarios
On 23.07.2019 15:44, Juergen Gross wrote:
> On 23.07.19 14:42, Jan Beulich wrote:
>> v->processor gets latched into st->processor before raising the softirq,
>> but can't the vCPU be moved elsewhere by the time the softirq handler
>> actually gains control? If that's not possible (and if it's not obvious
>> why, and as you can see it's not obvious to me), then I think a code
>> comment wants to be added there.
>
> You are right, it might be possible for the vcpu to move around.
>
> OTOH is it really important to run the target vcpu exactly on the cpu
> it is executing (or has last executed) at the time the NMI/MCE is being
> queued? This is in no way related to the cpu the MCE or NMI has been
> happening on. It is just a random cpu, and so it would be if we'd do the
> cpu selection when the softirq handler is running.
>
> One question to understand the idea nehind all that: _why_ is the vcpu
> pinned until it does an iret? I could understand if it would be pinned
> to the cpu where the NMI/MCE was happening, but this is not the case.
Then it was never finished or got broken, I would guess. Especially for
#MC the idea is/was for the domain to be able to access the MSRs in
question (). Iirc, that is, and prior to vMCE appearing.
Jan
_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxxx
https://lists.xenproject.org/mailman/listinfo/xen-devel
|