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Re: [Xen-devel] [PATCH v3 03/14] AMD/IOMMU: use bit field for control register
- To: "Woods, Brian" <Brian.Woods@xxxxxxx>
- From: Jan Beulich <JBeulich@xxxxxxxx>
- Date: Mon, 22 Jul 2019 08:55:45 +0000
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Suravee Suthikulpanit <Suravee.Suthikulpanit@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Mon, 22 Jul 2019 09:00:29 +0000
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- Thread-topic: [PATCH v3 03/14] AMD/IOMMU: use bit field for control register
On 19.07.2019 20:23, Woods, Brian wrote:
> On Tue, Jul 16, 2019 at 04:36:06PM +0000, Jan Beulich wrote:
>> Also introduce a field in struct amd_iommu caching the most recently
>> written control register. All writes should now happen exclusively from
>> that cached value, such that it is guaranteed to be up to date.
>>
>> Take the opportunity and add further fields. Also convert a few boolean
>> function parameters to bool, such that use of !! can be avoided.
>>
>> Because of there now being definitions beyond bit 31, writel() also gets
>> replaced by writeq() when updating hardware.
>>
>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
>> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
>
> Acked-by: Brian Woods <brian.woods@xxxxxxx>
Thanks for this and the other acks. I notice though that you skipped
patches 2 and 13: Are there concerns there? Patch 8 still has a
discussion to settle, so I realize you probably wouldn't want to ack
that one yet.
Jan
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