Re: [Xen-devel] [PATCH v8 49/50] x86emul: add a SHA test case to the harness

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

On 15/03/2019 11:08, Jan Beulich wrote:
> +        /*
> +         * SHA256RNDS2
> +         *
> +         * SRC1 = { C0, D0, G0, H0 }
> +         * SRC2 = { A0, B0, E0, F0 }
> +         * XMM0 = W' = { ?, ?, WK1, WK0 }
> +         *
> +         * (NB that the notation again is not C-like, i.e. elements are 
> listed
> +         * high-to-low everywhere in this comment.)
> +         *
> +         * Ch(E,F,G) = (E & F) ^ (~E & G)
> +         * Maj(A,B,C) = (A & B) ^ (A & C) ^ (B & C)
> +         *
> +         * Σ0(A) = ROR2(A) ^ ROR13(A) ^ ROR22(A)
> +         * Σ1(E) = ROR6(E) ^ ROR11(E) ^ ROR25(E)

This looks like some encoding problems (and later on in the comment).  I
can't tell whether it is a consequence of the email or something present
in the underlying patch. 

> --- a/tools/tests/x86_emulator/test_x86_emulator.c
> +++ b/tools/tests/x86_emulator/test_x86_emulator.c
> @@ -155,6 +158,21 @@ static bool simd_check_avx512vbmi_vl(voi
>      return cpu_has_avx512_vbmi && cpu_has_avx512vl;
>  }
>  
> +static bool simd_check_sse4_sha(void)
> +{
> +    return cpu_has_sha && cpu_has_sse4_2;

The legacy instruction isn't listed as having any dependency other than
the SHA bit.

> +}
> +
> +static bool simd_check_avx_sha(void)
> +{
> +    return cpu_has_sha && cpu_has_avx;

I can't locate any [E]VEX encoding information for the SHA
instructions.  Is this a side effect of the rest of the test algorithm,
or am I missing something in the manual?

~Andrew

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