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Re: [Xen-devel] [PATCH V2 3/3] xen/arm: Add SCIFA UART support for early printk



Hi Julien

Actually, the main difference for the "early printk" support is in two reg offsets:

+#define SCIFA_SCASSR   0x14    /* Serial status register */
+#define SCIFA_SCAFTDR  0x20    /* Transmit FIFO data register */

+#define SCIF_SCFSR             0x10    /* Serial status register */
+#define SCIF_SCFTDR            0x0c    /* Transmit FIFO data register */


I am not mistaken, we will have to introduce two options to cover this case, as the offsets are not correlated with each other, no?

You don't need two options. For instance, you can only introduce an option SCIF_VERSION that would be 0 for SCIF and 61 (ascii 'a') for SCIFA.

Then in the code, you can use SCIF_VERSION to decides which sets of macros you are using.

I think I understand the idea. Will try.


Is it something you would like to see?

[Sorry for formatting]


---
 xen/arch/arm/Rules.mk             |  7 +++++++
 xen/arch/arm/arm32/debug-scif.inc | 22 +++++++++++++++-------
 2 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk
index f264592..b29bd60 100644
--- a/xen/arch/arm/Rules.mk
+++ b/xen/arch/arm/Rules.mk
@@ -69,6 +69,12 @@ EARLY_PRINTK_BAUD := $(word 3,$(EARLY_PRINTK_CFG))
 endif
 endif

+# For the debug-scif.inc to recognize which UART offsets to apply
+ifeq ($(EARLY_PRINTK_INC),scifa)
+EARLY_PRINTK_SCIFA_OPTION := y
+EARLY_PRINTK_INC := scif
+endif
+
 ifneq ($(EARLY_PRINTK_INC),)
 EARLY_PRINTK := y
 endif
@@ -79,6 +85,7 @@ CFLAGS-$(EARLY_PRINTK) += -DEARLY_PRINTK_INC=\"debug-$(EARLY_PRINTK_INC).inc\"
 CFLAGS-$(EARLY_PRINTK) += -DEARLY_PRINTK_BAUD=$(EARLY_PRINTK_BAUD)
 CFLAGS-$(EARLY_PRINTK) += -DEARLY_UART_BASE_ADDRESS=$(EARLY_UART_BASE_ADDRESS)
 CFLAGS-$(EARLY_PRINTK) += -DEARLY_UART_REG_SHIFT=$(EARLY_UART_REG_SHIFT)
+CFLAGS-$(EARLY_PRINTK_SCIFA_OPTION) += -DEARLY_PRINTK_SCIFA_OPTION

 else # !CONFIG_DEBUG

diff --git a/xen/arch/arm/arm32/debug-scif.inc b/xen/arch/arm/arm32/debug-scif.inc
index 143f05d..49df616 100644
--- a/xen/arch/arm/arm32/debug-scif.inc
+++ b/xen/arch/arm/arm32/debug-scif.inc
@@ -1,7 +1,7 @@
 /*
  * xen/arch/arm/arm32/debug-scif.inc
  *
- * SCIF specific debug code
+ * SCIF(A) specific debug code
  *
  * Oleksandr Tyshchenko <oleksandr.tyshchenko@xxxxxxxxxxxxxxx>
  * Copyright (C) 2014, Globallogic.
@@ -19,28 +19,36 @@

 #include <asm/scif-uart.h>

+#ifdef EARLY_PRINTK_SCIFA_OPTION
+#define STATUS_REG    SCIFA_SCASSR
+#define TX_FIFO_REG   SCIFA_SCAFTDR
+#else
+#define STATUS_REG    SCIF_SCFSR
+#define TX_FIFO_REG   SCIF_SCFTDR
+#endif
+
 /*
- * SCIF UART wait UART to be ready to transmit
+ * SCIF(A) UART wait UART to be ready to transmit
  * rb: register which contains the UART base address
  * rc: scratch register
  */
 .macro early_uart_ready rb rc
 1:
-        ldrh   \rc, [\rb, #SCIF_SCFSR]   /* <- SCFSR (status register) */
+        ldrh   \rc, [\rb, #STATUS_REG]   /* Read status register */
         tst    \rc, #SCFSR_TDFE          /* Check TDFE bit */
         beq    1b                        /* Wait for the UART to be ready */
 .endm

 /*
- * SCIF UART transmit character
+ * SCIF(A) UART transmit character
  * rb: register which contains the UART base address
  * rt: register which contains the character to transmit
  */
 .macro early_uart_transmit rb rt
-        strb   \rt, [\rb, #SCIF_SCFTDR]                  /* -> SCFTDR (data register) */ -        ldrh   \rt, [\rb, #SCIF_SCFSR]                   /* <- SCFSR (status register) */ +        strb   \rt, [\rb, #TX_FIFO_REG]                  /* Write data register */ +        ldrh   \rt, [\rb, #STATUS_REG]                   /* Read status register */          and    \rt, \rt, #(~(SCFSR_TEND | SCFSR_TDFE))   /* Clear TEND and TDFE bits */ -        strh   \rt, [\rb, #SCIF_SCFSR]                   /* -> SCFSR (status register) */ +        strh   \rt, [\rb, #STATUS_REG]                   /* Write status register */
 .endm

 /*
--
2.7.4




--
Regards,

Oleksandr Tyshchenko


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