[Xen-devel] [RFC v2 12/16] gic-v2: avoid HCR reading for GICv2

[Andrii Anisov <andrii.anisov@xxxxxxxxx>]

From: Andrii Anisov <andrii_anisov@xxxxxxxx>

Because the HCR value is only changed by the hypervisor,
we can rely on a cached value and do not do peripheral register
reads for this register.

Signed-off-by: Andrii Anisov <andrii_anisov@xxxxxxxx>
---
 xen/arch/arm/gic-v2.c     | 43 +++++++++++++++++++++++++------------------
 xen/arch/arm/gic-v3.c     |  2 +-
 xen/include/asm-arm/gic.h |  2 +-
 3 files changed, 27 insertions(+), 20 deletions(-)

diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 25147bd..cc7571e 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -174,6 +174,28 @@ static unsigned int gicv2_cpu_mask(const cpumask_t 
*cpumask)
     return mask;
 }
 
+static void _gicv2_hcr_status(struct vcpu *v, uint32_t flag, bool status)
+{
+    uint32_t hcr, ohcr;
+
+    ohcr = hcr = v->arch.gic.v2.hcr;
+
+    if ( status )
+        hcr |= flag;
+    else
+        hcr &= (~flag);
+
+    if ( hcr != ohcr )
+        writel_gich(hcr, GICH_HCR);
+
+     v->arch.gic.v2.hcr = hcr;
+}
+
+static void gicv2_hcr_status(uint32_t flag, bool status)
+{
+    _gicv2_hcr_status(current, flag, status);
+}
+
 static void gicv2_save_state(struct vcpu *v)
 {
     int i;
@@ -188,10 +210,10 @@ static void gicv2_save_state(struct vcpu *v)
     v->arch.gic.v2.apr = readl_gich(GICH_APR);
     v->arch.gic.v2.vmcr = readl_gich(GICH_VMCR);
     /* Disable until next VCPU scheduled */
-    writel_gich(0, GICH_HCR);
+    _gicv2_hcr_status(v, GICH_HCR_EN, false);
 }
 
-static void gicv2_restore_state(const struct vcpu *v)
+static void gicv2_restore_state(struct vcpu *v)
 {
     int i;
 
@@ -200,7 +222,7 @@ static void gicv2_restore_state(const struct vcpu *v)
 
     writel_gich(v->arch.gic.v2.apr, GICH_APR);
     writel_gich(v->arch.gic.v2.vmcr, GICH_VMCR);
-    writel_gich(GICH_HCR_EN, GICH_HCR);
+    _gicv2_hcr_status(v, GICH_HCR_EN, true);
 }
 
 static void gicv2_dump_state(const struct vcpu *v)
@@ -577,21 +599,6 @@ static void gicv2_write_lr(int lr, const struct gic_lr 
*lr_reg)
     writel_gich(lrv, GICH_LR + lr * 4);
 }
 
-static void gicv2_hcr_status(uint32_t flag, bool status)
-{
-    uint32_t hcr, ohcr;
-
-    ohcr = hcr = readl_gich(GICH_HCR);
-
-    if ( status )
-        hcr |= flag;
-    else
-        hcr &= (~flag);
-
-    if ( hcr != ohcr )
-        writel_gich(hcr, GICH_HCR);
-}
-
 static unsigned int gicv2_read_vmcr_priority(void)
 {
    return ((readl_gich(GICH_VMCR) >> GICH_V2_VMCR_PRIORITY_SHIFT)
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 8e835b5..6269425 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -377,7 +377,7 @@ static void gicv3_save_state(struct vcpu *v)
     v->arch.gic.v3.sre_el1 = READ_SYSREG32(ICC_SRE_EL1);
 }
 
-static void gicv3_restore_state(const struct vcpu *v)
+static void gicv3_restore_state(struct vcpu *v)
 {
     uint32_t val;
 
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 3d7394d..ea9bbed 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -323,7 +323,7 @@ struct gic_hw_operations {
     /* Save GIC registers */
     void (*save_state)(struct vcpu *);
     /* Restore GIC registers */
-    void (*restore_state)(const struct vcpu *);
+    void (*restore_state)(struct vcpu *);
     /* Dump GIC LR register information */
     void (*dump_state)(const struct vcpu *);
 
-- 
2.7.4


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