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Re: [Xen-devel] Xen 4.12 Development Update
- To: Juergen Gross <jgross@xxxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Fri, 9 Nov 2018 11:44:44 +0000
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- Delivery-date: Fri, 09 Nov 2018 11:44:51 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Openpgp: preference=signencrypt
On 09/11/18 10:16, Juergen Gross wrote:
> = Projects =
>
> == Hypervisor ==
>
> * Improvements to domain creation (v2)
> - Andrew Cooper
There is one known bug which definitely needs resolving before 4.12 goes
out. Attempting to create a VM with 0 vcpus trips over a bad error path
when we try to remove permissions for an irq which we never gave in the
first place. The fix is most likely to not change irq permissions on unmap.
Beyond that, the next actions are to make the create/destroy paths
idempotent. If anyone feels like helping out here, please do.
After that, DOMCTL_max_vcpus needs to be folded into the create path.
An orthogonal task, which really also needs doing before 4.12 goes out
is to rearrange the point at which d->max_cpus is calculated, so ARM
gets this number early enough in construction to properly build the
GIC. (At the moment, there is a bait-and-switch to defer GIC
construction until the first vcpu is being constructed).
> === x86 ===
* Fixes to #DB injection
This is also a swamp. Already done:
1) Fixes to vcpu register initialisation
Still to do:
2) Rework monitor hooking to avoid livelocks with a fixed #DB
3) Plumb pending_dbg into x86_event, including reporting properly in monitor
4) Fix xen_dm_op_inject_event to audit its data rather than causing a
vmentry failure
5) Fix merging of new bits into %dr6
6) Fix singlestepping to not result in a vmentry failure when in an STI
shadow
$N) Pester Intel some more as to why a vmexit with both singlestep and
breakpoint events pending loses architectural information.
Also, the big one.
* CPUID/MSR Xen/toolstack improvements
This is blocking an enormous quantity of work, included but not limited to:
1) Fixing topology layout. Unblocks the >127 vcpu work, and core-aware
scheduling work.
2) Virtusalising features which MSRs for configuration, including
nested-VTx, SGX, Intel PT and MSR_ARCH_CAPS.
~Andrew
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