Re: [Xen-devel] Interrupt injection with ISR set on Intel hardware

["Tian, Kevin" <kevin.tian@xxxxxxxxx>]

> From: Jan Beulich [mailto:JBeulich@xxxxxxxx]
> Sent: Thursday, October 25, 2018 9:58 PM
> 
> >>> On 25.10.18 at 15:02, <andrew.cooper3@xxxxxxxxxx> wrote:
> > On 25/10/18 13:51, Jan Beulich wrote:
> >>>>> On 15.10.18 at 14:06, <andrew.cooper3@xxxxxxxxxx> wrote:
> >>> From the debugging, we see that PPR/IRR/ISR appear to retain their
> state
> >>> across the mwait, and there is nothing in the manual which I can see
> >>> discussing the interaction of LAPIC state and C states.
> >> Is it perhaps a bad idea to go idle with an un-acked interrupt?
> >
> > Most likely.
> >
> > Then again, going idle with an un-acked line interrupt does appear to
> > work.  It is only un-acked edge interrupts which appear to hit this issue.
> 
> Well, non-maskable MSI are the only ones (outside of "new" IO-APIC
> ack mode, which should not be used on recent hardware because of
> directed EOI presumably being available everywhere) where the ack
> gets deferred until the .end hook (i.e. after the handler was run).
> IOW AFAICT line interrupts would never be pending when we go idle.
> 
> > Still - I'd prefer some guidance from the hardware folk as to what can
> > realistically be expected here.
> 
> Fully agree.

Just sent a mail internally to get clarification.

Thanks
Kevin

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