[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 05/22] xen/arm: Consolidate CPU identification in cpufeature.{c, h}
At the moment, CPU Identification is spread accross cpu.c, cpufeature.c, processor.h, cpufeature.h. It would be better to keep everything together in a single place. Signed-off-by: Julien Grall <julien.grall@xxxxxxx> --- xen/arch/arm/Makefile | 1 - xen/arch/arm/cpu.c | 68 -------------------- xen/arch/arm/cpufeature.c | 42 ++++++++++++ xen/arch/arm/vcpreg.c | 1 + xen/include/asm-arm/cpufeature.h | 134 ++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/processor.h | 135 --------------------------------------- 6 files changed, 177 insertions(+), 204 deletions(-) delete mode 100644 xen/arch/arm/cpu.c diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 37fa8268b3..6d91ba7c46 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -6,7 +6,6 @@ subdir-$(CONFIG_ACPI) += acpi obj-$(CONFIG_HAS_ALTERNATIVE) += alternative.o obj-y += bootfdt.init.o -obj-y += cpu.o obj-y += cpuerrata.o obj-y += cpufeature.o obj-y += decode.o diff --git a/xen/arch/arm/cpu.c b/xen/arch/arm/cpu.c deleted file mode 100644 index 9595f1d63a..0000000000 --- a/xen/arch/arm/cpu.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <xen/init.h> -#include <xen/lib.h> -#include <xen/sched.h> - -#include <asm/processor.h> - -void identify_cpu(struct cpuinfo_arm *c) -{ - c->midr.bits = READ_SYSREG32(MIDR_EL1); - c->mpidr.bits = READ_SYSREG(MPIDR_EL1); - -#ifdef CONFIG_ARM_64 - c->pfr64.bits[0] = READ_SYSREG64(ID_AA64PFR0_EL1); - c->pfr64.bits[1] = READ_SYSREG64(ID_AA64PFR1_EL1); - - c->dbg64.bits[0] = READ_SYSREG64(ID_AA64DFR0_EL1); - c->dbg64.bits[1] = READ_SYSREG64(ID_AA64DFR1_EL1); - - c->aux64.bits[0] = READ_SYSREG64(ID_AA64AFR0_EL1); - c->aux64.bits[1] = READ_SYSREG64(ID_AA64AFR1_EL1); - - c->mm64.bits[0] = READ_SYSREG64(ID_AA64MMFR0_EL1); - c->mm64.bits[1] = READ_SYSREG64(ID_AA64MMFR1_EL1); - - c->isa64.bits[0] = READ_SYSREG64(ID_AA64ISAR0_EL1); - c->isa64.bits[1] = READ_SYSREG64(ID_AA64ISAR1_EL1); -#endif - - c->pfr32.bits[0] = READ_SYSREG32(ID_PFR0_EL1); - c->pfr32.bits[1] = READ_SYSREG32(ID_PFR1_EL1); - - c->dbg32.bits[0] = READ_SYSREG32(ID_DFR0_EL1); - - c->aux32.bits[0] = READ_SYSREG32(ID_AFR0_EL1); - - c->mm32.bits[0] = READ_SYSREG32(ID_MMFR0_EL1); - c->mm32.bits[1] = READ_SYSREG32(ID_MMFR1_EL1); - c->mm32.bits[2] = READ_SYSREG32(ID_MMFR2_EL1); - c->mm32.bits[3] = READ_SYSREG32(ID_MMFR3_EL1); - - c->isa32.bits[0] = READ_SYSREG32(ID_ISAR0_EL1); - c->isa32.bits[1] = READ_SYSREG32(ID_ISAR1_EL1); - c->isa32.bits[2] = READ_SYSREG32(ID_ISAR2_EL1); - c->isa32.bits[3] = READ_SYSREG32(ID_ISAR3_EL1); - c->isa32.bits[4] = READ_SYSREG32(ID_ISAR4_EL1); - c->isa32.bits[5] = READ_SYSREG32(ID_ISAR5_EL1); -} - -/* - * Local variables: - * mode: C - * c-file-style: "BSD" - * c-basic-offset: 4 - * indent-tabs-mode: nil - * End: - */ diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c index 3aaff4c0e6..44126dbf07 100644 --- a/xen/arch/arm/cpufeature.c +++ b/xen/arch/arm/cpufeature.c @@ -97,6 +97,48 @@ int enable_nonboot_cpu_caps(const struct arm_cpu_capabilities *caps) return rc; } +void identify_cpu(struct cpuinfo_arm *c) +{ + c->midr.bits = READ_SYSREG32(MIDR_EL1); + c->mpidr.bits = READ_SYSREG(MPIDR_EL1); + +#ifdef CONFIG_ARM_64 + c->pfr64.bits[0] = READ_SYSREG64(ID_AA64PFR0_EL1); + c->pfr64.bits[1] = READ_SYSREG64(ID_AA64PFR1_EL1); + + c->dbg64.bits[0] = READ_SYSREG64(ID_AA64DFR0_EL1); + c->dbg64.bits[1] = READ_SYSREG64(ID_AA64DFR1_EL1); + + c->aux64.bits[0] = READ_SYSREG64(ID_AA64AFR0_EL1); + c->aux64.bits[1] = READ_SYSREG64(ID_AA64AFR1_EL1); + + c->mm64.bits[0] = READ_SYSREG64(ID_AA64MMFR0_EL1); + c->mm64.bits[1] = READ_SYSREG64(ID_AA64MMFR1_EL1); + + c->isa64.bits[0] = READ_SYSREG64(ID_AA64ISAR0_EL1); + c->isa64.bits[1] = READ_SYSREG64(ID_AA64ISAR1_EL1); +#endif + + c->pfr32.bits[0] = READ_SYSREG32(ID_PFR0_EL1); + c->pfr32.bits[1] = READ_SYSREG32(ID_PFR1_EL1); + + c->dbg32.bits[0] = READ_SYSREG32(ID_DFR0_EL1); + + c->aux32.bits[0] = READ_SYSREG32(ID_AFR0_EL1); + + c->mm32.bits[0] = READ_SYSREG32(ID_MMFR0_EL1); + c->mm32.bits[1] = READ_SYSREG32(ID_MMFR1_EL1); + c->mm32.bits[2] = READ_SYSREG32(ID_MMFR2_EL1); + c->mm32.bits[3] = READ_SYSREG32(ID_MMFR3_EL1); + + c->isa32.bits[0] = READ_SYSREG32(ID_ISAR0_EL1); + c->isa32.bits[1] = READ_SYSREG32(ID_ISAR1_EL1); + c->isa32.bits[2] = READ_SYSREG32(ID_ISAR2_EL1); + c->isa32.bits[3] = READ_SYSREG32(ID_ISAR3_EL1); + c->isa32.bits[4] = READ_SYSREG32(ID_ISAR4_EL1); + c->isa32.bits[5] = READ_SYSREG32(ID_ISAR5_EL1); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index b04d996fd3..7b783e4bcc 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -18,6 +18,7 @@ #include <xen/sched.h> +#include <asm/cpufeature.h> #include <asm/cpregs.h> #include <asm/current.h> #include <asm/regs.h> diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 2d82264427..17de928467 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -104,6 +104,140 @@ void update_cpu_capabilities(const struct arm_cpu_capabilities *caps, void enable_cpu_capabilities(const struct arm_cpu_capabilities *caps); int enable_nonboot_cpu_caps(const struct arm_cpu_capabilities *caps); +/* + * capabilities of CPUs + */ +struct cpuinfo_arm { + union { + uint32_t bits; + struct { + unsigned long revision:4; + unsigned long part_number:12; + unsigned long architecture:4; + unsigned long variant:4; + unsigned long implementer:8; + }; + } midr; + union { + register_t bits; + struct { + unsigned long aff0:8; + unsigned long aff1:8; + unsigned long aff2:8; + unsigned long mt:1; /* Multi-thread, iff MP == 1 */ + unsigned long __res0:5; + unsigned long up:1; /* UP system, iff MP == 1 */ + unsigned long mp:1; /* MP extensions */ + +#ifdef CONFIG_ARM_64 + unsigned long aff3:8; + unsigned long __res1:24; +#endif + }; + } mpidr; + +#ifdef CONFIG_ARM_64 + /* 64-bit CPUID registers. */ + union { + uint64_t bits[2]; + struct { + unsigned long el0:4; + unsigned long el1:4; + unsigned long el2:4; + unsigned long el3:4; + unsigned long fp:4; /* Floating Point */ + unsigned long simd:4; /* Advanced SIMD */ + unsigned long gic:4; /* GIC support */ + unsigned long __res0:28; + unsigned long csv2:4; + unsigned long __res1:4; + }; + } pfr64; + + struct { + uint64_t bits[2]; + } dbg64; + + struct { + uint64_t bits[2]; + } aux64; + + union { + uint64_t bits[2]; + struct { + unsigned long pa_range:4; + unsigned long asid_bits:4; + unsigned long bigend:4; + unsigned long secure_ns:4; + unsigned long bigend_el0:4; + unsigned long tgranule_16K:4; + unsigned long tgranule_64K:4; + unsigned long tgranule_4K:4; + unsigned long __res0:32; + + unsigned long hafdbs:4; + unsigned long vmid_bits:4; + unsigned long vh:4; + unsigned long hpds:4; + unsigned long lo:4; + unsigned long pan:4; + unsigned long __res1:8; + unsigned long __res2:32; + }; + } mm64; + + struct { + uint64_t bits[2]; + } isa64; + +#endif + + /* + * 32-bit CPUID registers. On ARMv8 these describe the properties + * when running in 32-bit mode. + */ + union { + uint32_t bits[2]; + struct { + unsigned long arm:4; + unsigned long thumb:4; + unsigned long jazelle:4; + unsigned long thumbee:4; + unsigned long __res0:16; + + unsigned long progmodel:4; + unsigned long security:4; + unsigned long mprofile:4; + unsigned long virt:4; + unsigned long gentimer:4; + unsigned long __res1:12; + }; + } pfr32; + + struct { + uint32_t bits[1]; + } dbg32; + + struct { + uint32_t bits[1]; + } aux32; + + struct { + uint32_t bits[4]; + } mm32; + + struct { + uint32_t bits[6]; + } isa32; +}; + +extern struct cpuinfo_arm boot_cpu_data; + +extern void identify_cpu(struct cpuinfo_arm *); + +extern struct cpuinfo_arm cpu_data[]; +#define current_cpu_data cpu_data[smp_processor_id()] + #endif /* __ASSEMBLY__ */ #endif diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index efa33b4665..f7a2e9a3ad 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -350,141 +350,6 @@ #ifndef __ASSEMBLY__ -struct cpuinfo_arm { - union { - uint32_t bits; - struct { - unsigned long revision:4; - unsigned long part_number:12; - unsigned long architecture:4; - unsigned long variant:4; - unsigned long implementer:8; - }; - } midr; - union { - register_t bits; - struct { - unsigned long aff0:8; - unsigned long aff1:8; - unsigned long aff2:8; - unsigned long mt:1; /* Multi-thread, iff MP == 1 */ - unsigned long __res0:5; - unsigned long up:1; /* UP system, iff MP == 1 */ - unsigned long mp:1; /* MP extensions */ - -#ifdef CONFIG_ARM_64 - unsigned long aff3:8; - unsigned long __res1:24; -#endif - }; - } mpidr; - -#ifdef CONFIG_ARM_64 - /* 64-bit CPUID registers. */ - union { - uint64_t bits[2]; - struct { - unsigned long el0:4; - unsigned long el1:4; - unsigned long el2:4; - unsigned long el3:4; - unsigned long fp:4; /* Floating Point */ - unsigned long simd:4; /* Advanced SIMD */ - unsigned long gic:4; /* GIC support */ - unsigned long __res0:28; - unsigned long csv2:4; - unsigned long __res1:4; - }; - } pfr64; - - struct { - uint64_t bits[2]; - } dbg64; - - struct { - uint64_t bits[2]; - } aux64; - - union { - uint64_t bits[2]; - struct { - unsigned long pa_range:4; - unsigned long asid_bits:4; - unsigned long bigend:4; - unsigned long secure_ns:4; - unsigned long bigend_el0:4; - unsigned long tgranule_16K:4; - unsigned long tgranule_64K:4; - unsigned long tgranule_4K:4; - unsigned long __res0:32; - - unsigned long hafdbs:4; - unsigned long vmid_bits:4; - unsigned long vh:4; - unsigned long hpds:4; - unsigned long lo:4; - unsigned long pan:4; - unsigned long __res1:8; - unsigned long __res2:32; - }; - } mm64; - - struct { - uint64_t bits[2]; - } isa64; - -#endif - - /* - * 32-bit CPUID registers. On ARMv8 these describe the properties - * when running in 32-bit mode. - */ - union { - uint32_t bits[2]; - struct { - unsigned long arm:4; - unsigned long thumb:4; - unsigned long jazelle:4; - unsigned long thumbee:4; - unsigned long __res0:16; - - unsigned long progmodel:4; - unsigned long security:4; - unsigned long mprofile:4; - unsigned long virt:4; - unsigned long gentimer:4; - unsigned long __res1:12; - }; - } pfr32; - - struct { - uint32_t bits[1]; - } dbg32; - - struct { - uint32_t bits[1]; - } aux32; - - struct { - uint32_t bits[4]; - } mm32; - - struct { - uint32_t bits[6]; - } isa32; -}; - -/* - * capabilities of CPUs - */ - -extern struct cpuinfo_arm boot_cpu_data; - -extern void identify_cpu(struct cpuinfo_arm *); - -extern struct cpuinfo_arm cpu_data[]; -#define current_cpu_data cpu_data[smp_processor_id()] - extern register_t __cpu_logical_map[]; #define cpu_logical_map(cpu) __cpu_logical_map[cpu] -- 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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