[Xen-devel] [PATCH 09/17] x86/amd: put setting pv_post_outb_hook under CONFIG_PV

[Wei Liu <wei.liu2@xxxxxxxxxx>]

It is used by PV code only.

Signed-off-by: Wei Liu <wei.liu2@xxxxxxxxxx>
---
 xen/arch/x86/cpu/amd.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index c394c1c..5e2112e 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -443,12 +443,14 @@ static void disable_c1e(void *unused)
                       smp_processor_id(), msr_content);
 }
 
+#ifdef CONFIG_PV
 static void check_disable_c1e(unsigned int port, u8 value)
 {
        /* C1E is sometimes enabled during entry to ACPI mode. */
        if ((port == acpi_smi_cmd) && (value == acpi_enable_value))
                on_each_cpu(disable_c1e, NULL, 1);
 }
+#endif
 
 /*
  * BIOS is expected to clear MtrrFixDramModEn bit. According to AMD BKDG : 
@@ -627,8 +629,10 @@ static void init_amd(struct cpuinfo_x86 *c)
        {
        case 0xf ... 0x17:
                disable_c1e(NULL);
+#ifdef CONFIG_PV
                if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value))
                        pv_post_outb_hook = check_disable_c1e;
+#endif
                break;
        }
 
-- 
git-series 0.9.1

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