Re: [Xen-devel] [PATCH 5/6] x86/HVM: prefill cache with PDPTEs when possible

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 24.07.18 at 09:27, <jgross@xxxxxxxx> wrote:
> On 24/07/18 09:04, Jan Beulich wrote:
>>>>> On 19.07.18 at 21:07, <andrew.cooper3@xxxxxxxxxx> wrote:
>>> Oh - I'd not looked in that much detail at your algorithm.  As a first
>>> gut feel, tagging by level doesn't sound as if it will interact
>>> correctly with linear pagetables.
>>>
>>> Both the Intel and AMD ORM's maintain paging structure caches so I'd
>>> expect that a linear pagetable entry would be served from that cache
>>> rather than being read twice from RAM.
>> 
>> Is there anywhere enough detail about the actual implementation of
>> the paging structure caches? I could imagine them being per level. It
>> wouldn't be very difficult to switch to a tristate here (normal data,
>> page table, and PAE L3).
>> 
> 
> From https://www.cs.rice.edu/CS/Architecture/docs/barr-isca10.pdf :
> 
> Therefore, both AMD and Intel have implemented MMU
> caches for page table entries from the higher levels of the tree [3,
> 9]. However, their caches have quite different structure. For exam-
> ple, AMD’s Page Walk Cache stores page table entries from any
> level of the tree, whereas Intel implements distinct caches for each
> level  of  the  tree.   Also,  AMD’s  Page  Walk  Cache  is  indexed  by
> the physical address of the cached page table entry, whereas Intel’s
> Paging-Structure Caches are indexed by portions of the virtual ad-
> dress being translated

Oh, interesting, thanks. Basically means OSes and alike can't really
rely on any specific behavior, and implementations have some
leeway.

Jan


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