Re: [Xen-devel] [PATCH v3] x86/mm: Add mem access rights to NPT

["Jan Beulich" <jbeulich@xxxxxxxx>]

>>> Tamas K Lengyel <tamas@xxxxxxxxxxxxx> 07/19/18 5:09 PM >>>
>On Thu, Jul 19, 2018 at 2:30 AM Jan Beulich <JBeulich@xxxxxxxx> wrote:
> >>> On 19.07.18 at 10:18, <aisaila@xxxxxxxxxxxxxxx> wrote:
> > On Mi, 2018-07-18 at 15:33 +0000, George Dunlap wrote:
> >> > On Jul 2, 2018, at 8:42 AM, Alexandru Isaila <aisaila@bitdefender.c
>> >> > +            break;
>> >> > +        case p2m_access_x:
>> >> > +            flags &= ~_PAGE_RW;
>> >> > +            break;
>> >> > +        case p2m_access_rwx:
>> >> > +        default:
>> >> > +            break;
>> >> >     }
>> >> I think you want another blank line here too.
>> >>
>> >> Also, this doesn’t seem to capture the ‘r’ part of the equation —
>> >> shouldn’t p2m_access_n end up with a not-present p2m entry?
>> >
>> > SVM dosen't explicitly provide a read access bit so we treat read and
>> > write the same way.
>>
>> Read and write can't possibly be treated the same. You ought to use
>> the present bit to deny read (really: any) access, as also implied by
>> George's response.
>
>We already treat write accesses also as read on Intel because of
>hardware limitations with CMPXCHG. So I don't see a problem with this.

Right - write implies read. Which means no-read implies no-write. Which
still means to me that p2m_access_n can't result in other than a not-
present entry.

Jan




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