Re: [Xen-devel] [PATCH v2 10/10] x86: Handle new asynchronous exit qualification

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 30.05.18 at 15:28, <luwei.kang@xxxxxxxxx> wrote:
> Using EPT to translate PT output addresses introduces the possibility of
> taking events on PT output reads and writes. Event possibilities include
> EPT violations, EPT misconfigurations, PML log-full VM exits, and APIC
> access VM exits.
> EPT violations:
>  a. Intel PT buffer is a MMIO address in guest. Actually, it can be a
>     MMIO address (SDM 35.2.6.1), but in order do not affect other
>     passthrough/emulate device in guest. Ferbid use MMIO addr at present.
>  b. Intel PT buffer is a RAM non-writable address. Don't need emulate
>     and inject a #GP to guest.

Is such #GP injection architectural behavior? We've got a few bad
examples where we inject exceptions which are architecturally
impossible - let's please not add any further instances.

> @@ -4027,6 +4028,10 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs)
>          break;
>  
>      case EXIT_REASON_APIC_ACCESS:
> +        __vmread(EXIT_QUALIFICATION, &exit_qualification);
> +        if ( exit_qualification & 0x10000 )

Please no use of literal numbers like this.

Jan



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