[Xen-devel] [PATCH v3 09/17] arm64: vgic-v3: Add ICV_BPR0_EL1 handler

[Manish Jaggi <mjaggi@xxxxxxxxxxxxxxxxxx>]

This patch is ported to xen from linux commit:
423de85a98c2b50715a0784a74f6124fbc0b1548

Add a handler for reading/writing the guest's view of the ICC_BPR0_EL1
register, which is located in the ICH_VMCR_EL2.BPR0 field.

Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx>

diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index c067278499..f3b6e5367c 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -280,6 +280,33 @@ static void vgic_v3_write_bpr1(struct cpu_user_regs *regs, 
uint32_t vmcr,
     vgic_v3_write_vmcr(vmcr);
 }
 
+static void vgic_v3_read_bpr0(struct cpu_user_regs *regs, uint32_t vmcr,
+                              int rt)
+{
+    set_user_reg(regs, rt, vgic_v3_get_bpr0(vmcr));
+}
+
+static void vgic_v3_write_bpr0(struct cpu_user_regs *regs, uint32_t vmcr,
+                               int rt)
+{
+    register_t val = get_user_reg(regs, rt);
+    uint8_t bpr_min = vgic_v3_bpr_min();
+
+    if ( vmcr & ICH_VMCR_CBPR_MASK )
+        return;
+
+    /* Enforce BPR limiting */
+    if ( val < bpr_min )
+        val = bpr_min;
+
+    val <<= ICH_VMCR_BPR0_SHIFT;
+    val &= ICH_VMCR_BPR0_MASK;
+    vmcr &= ~ICH_VMCR_BPR0_MASK;
+    vmcr |= val;
+
+    vgic_v3_write_vmcr(vmcr);
+}
+
 static void vgic_v3_read_igrpen1(struct cpu_user_regs *regs, uint32_t vmcr,
                                  int rt)
 {
@@ -641,6 +668,13 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs 
*regs)
     switch ( sysreg )
     {
 
+    case HSR_SYSREG_ICC_BPR0_EL1:
+        if ( is_read )
+            fn = vgic_v3_read_bpr0;
+        else
+            fn = vgic_v3_write_bpr0;
+        break;
+
     case HSR_SYSREG_ICC_BPR1_EL1:
         if ( is_read )
             fn = vgic_v3_read_bpr1;
diff --git a/xen/include/asm-arm/arm64/sysregs.h 
b/xen/include/asm-arm/arm64/sysregs.h
index b9230fe795..e03b6edf4d 100644
--- a/xen/include/asm-arm/arm64/sysregs.h
+++ b/xen/include/asm-arm/arm64/sysregs.h
@@ -94,6 +94,7 @@
 #define HSR_SYSREG_ICC_IAR1_EL1   HSR_SYSREG(3,0,c12,c12,0)
 #define HSR_SYSREG_ICC_EOIR1_EL1  HSR_SYSREG(3,0,c12,c12,1)
 #define HSR_SYSREG_ICC_HPPIR1_EL1 HSR_SYSREG(3,0,c12,c12,2)
+#define HSR_SYSREG_ICC_BPR0_EL1          HSR_SYSREG(3,0,c12,c8,3)
 #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
 
 #define HSR_SYSREG_PMCR_EL0       HSR_SYSREG(3,3,c9,c12,0)
-- 
2.14.1


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