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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v2] x86/cpu: Add supports for zhaoxin x86 platform
From: DavidWang <davidwang@xxxxxxxxxxx>
Zhaoxin is a x86 IC designer. Its SOC products support both CPU
virtualization and I/O virtualization, which are compatible with Intel
VMX and VT-d respectively. Zhaoxin has 'Shanghai' CPU vendor ID.
Signed-off-by: DavidWang <davidwang@xxxxxxxxxxx>
---
xen/arch/x86/cpu/Makefile | 1 +
xen/arch/x86/cpu/common.c | 1 +
xen/arch/x86/cpu/intel_cacheinfo.c | 2 +-
xen/arch/x86/cpu/shanghai.c | 90 ++++++++++++++++++++++++++++++++++++++
xen/include/asm-x86/cpufeature.h | 1 +
xen/include/asm-x86/iommu.h | 2 +
xen/include/asm-x86/setup.h | 1 +
xen/include/asm-x86/x86-vendors.h | 3 +-
8 files changed, 99 insertions(+), 2 deletions(-)
create mode 100644 xen/arch/x86/cpu/shanghai.c
diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile
index 74f23ae..34a01ca 100644
--- a/xen/arch/x86/cpu/Makefile
+++ b/xen/arch/x86/cpu/Makefile
@@ -7,4 +7,5 @@ obj-y += common.o
obj-y += intel.o
obj-y += intel_cacheinfo.o
obj-y += mwait-idle.o
+obj-y += shanghai.o
obj-y += vpmu.o vpmu_amd.o vpmu_intel.o
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 0a452ae..02863c9 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -709,6 +709,7 @@ void __init early_cpu_init(void)
intel_cpu_init();
amd_init_cpu();
centaur_init_cpu();
+ shanghai_init_cpu();
early_cpu_detect();
}
diff --git a/xen/arch/x86/cpu/intel_cacheinfo.c
b/xen/arch/x86/cpu/intel_cacheinfo.c
index 101e297..a3aec13 100644
--- a/xen/arch/x86/cpu/intel_cacheinfo.c
+++ b/xen/arch/x86/cpu/intel_cacheinfo.c
@@ -103,7 +103,7 @@ int cpuid4_cache_lookup(int index, struct cpuid4_info
*this_leaf)
return 0;
}
-static int find_num_cache_leaves(void)
+int find_num_cache_leaves(void)
{
unsigned int eax, ebx, ecx, edx;
union _cpuid4_leaf_eax cache_eax;
diff --git a/xen/arch/x86/cpu/shanghai.c b/xen/arch/x86/cpu/shanghai.c
new file mode 100644
index 0000000..ac12ba3
--- /dev/null
+++ b/xen/arch/x86/cpu/shanghai.c
@@ -0,0 +1,90 @@
+#include <xen/bitops.h>
+#include <xen/init.h>
+#include <asm/processor.h>
+#include "cpu.h"
+
+void init_shanghai_cache(struct cpuinfo_x86 *c)
+{
+ unsigned int i = 0, l1d = 0, l1i = 0, l2 = 0, l3 = 0;
+ struct cpuid4_info leaf;
+ static bool is_initialized = false;
+ static unsigned int cache_leaves = 0;
+
+ if ( (!is_initialized) && (c->cpuid_level > 0x00000003) )
+ {
+ /* Init cache_leaves from boot CPU */
+ cache_leaves = find_num_cache_leaves();
+ is_initialized = true;
+ }
+
+ /* Use cpuid:0x00000004 to find the cache details */
+ for (i = 0; i < cache_leaves; i++)
+ {
+ if( c->cpuid_level <= 0x00000003 )
+ break;
+
+ if ( !cpuid4_cache_lookup(i, &leaf) )
+ {
+ switch( leaf.eax.split.level )
+ {
+ case 1:
+ if ( leaf.eax.split.type ==
CACHE_TYPE_DATA )
+ l1d = leaf.size/1024;
+ else if ( leaf.eax.split.type ==
CACHE_TYPE_INST )
+ l1i = leaf.size/1024;
+ break;
+ case 2:
+ l2 = leaf.size/1024;
+ break;
+ case 3:
+ l3 = leaf.size/1024;
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ if ( opt_cpu_info )
+ {
+ if ( l1i )
+ printk("CPU: L1 I cache: %dK", l1i);
+
+ if ( l1d )
+ printk(", L1 D cache: %dK\n", l1d);
+ else
+ printk("\n");
+
+ if ( l2 )
+ printk("CPU: L2 cache: %dK\n", l2);
+
+ if ( l3 )
+ printk("CPU: L3 cache: %dK\n", l3);
+ }
+
+ c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i + l1d));
+}
+
+static void init_shanghai(struct cpuinfo_x86 *c)
+{
+ if ( cpu_has(c, X86_FEATURE_ITSC) )
+ {
+ __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
+ __set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
+ __set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability);
+ }
+
+ init_shanghai_cache(c);
+}
+
+static const struct cpu_dev shanghai_cpu_dev = {
+ .c_vendor = " Shang",
+ .c_ident = {" Shanghai "},
+ .c_init = init_shanghai,
+};
+
+int __init shanghai_init_cpu(void)
+{
+ cpu_devs[X86_VENDOR_SHANGHAI] = &shanghai_cpu_dev;
+ return 0;
+}
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 4c62597..2175bd0 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -157,6 +157,7 @@ struct cpuid4_info {
};
int cpuid4_cache_lookup(int index, struct cpuid4_info *this_leaf);
+int find_num_cache_leaves(void);
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_I386_CPUFEATURE_H */
diff --git a/xen/include/asm-x86/iommu.h b/xen/include/asm-x86/iommu.h
index 14ad048..6a6d3bf 100644
--- a/xen/include/asm-x86/iommu.h
+++ b/xen/include/asm-x86/iommu.h
@@ -54,6 +54,7 @@ static inline const struct iommu_ops *iommu_get_ops(void)
switch ( boot_cpu_data.x86_vendor )
{
case X86_VENDOR_INTEL:
+ case X86_VENDOR_SHANGHAI:
return &intel_iommu_ops;
case X86_VENDOR_AMD:
return &amd_iommu_ops;
@@ -69,6 +70,7 @@ static inline int iommu_hardware_setup(void)
switch ( boot_cpu_data.x86_vendor )
{
case X86_VENDOR_INTEL:
+ case X86_VENDOR_SHANGHAI:
return intel_vtd_setup();
case X86_VENDOR_AMD:
return amd_iov_detect();
diff --git a/xen/include/asm-x86/setup.h b/xen/include/asm-x86/setup.h
index 19232af..2c2d9fd 100644
--- a/xen/include/asm-x86/setup.h
+++ b/xen/include/asm-x86/setup.h
@@ -23,6 +23,7 @@ int cyrix_init_cpu(void);
int nsc_init_cpu(void);
int centaur_init_cpu(void);
int transmeta_init_cpu(void);
+int shanghai_init_cpu(void);
void set_nr_cpu_ids(unsigned int max_cpus);
diff --git a/xen/include/asm-x86/x86-vendors.h
b/xen/include/asm-x86/x86-vendors.h
index cae5507..c53d0b9 100644
--- a/xen/include/asm-x86/x86-vendors.h
+++ b/xen/include/asm-x86/x86-vendors.h
@@ -7,7 +7,8 @@
#define X86_VENDOR_INTEL 0
#define X86_VENDOR_AMD 1
#define X86_VENDOR_CENTAUR 2
-#define X86_VENDOR_NUM 3
+#define X86_VENDOR_SHANGHAI 3
+#define X86_VENDOR_NUM 4
#define X86_VENDOR_UNKNOWN 0xff
#endif /* __XEN_X86_VENDORS_H__ */
--
2.7.4
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