[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v2 12/17] arm64: vgic-v3: Add misc Group-0 handlers
This patch is ported to xen from linux commit: eab0b2dc4f6f34147e3d10da49ab8032e15dbea0 (KVM: arm64: vgic-v3: Add misc Group-0 handlers) A number of Group-0 registers can be handled by the same accessors as that of Group-1, so let's add the required system register encodings and catch them in the dispatching function. Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx> --- xen/arch/arm/arm64/vgic-v3-sr.c | 7 +++++++ xen/include/asm-arm/arm64/sysregs.h | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index d854b1070d..201194c713 100644 --- a/xen/arch/arm/arm64/vgic-v3-sr.c +++ b/xen/arch/arm/arm64/vgic-v3-sr.c @@ -793,30 +793,37 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs) vreg_emulate_igrpen1(regs, hsr); break; + case HSR_SYSREG_ICC_IAR0_EL1: case HSR_SYSREG_ICC_IAR1_EL1: vreg_emulate_iar(regs, hsr); break; + case HSR_SYSREG_ICC_EOIR0_EL1: case HSR_SYSREG_ICC_EOIR1_EL1: vreg_emulate_eoi(regs, hsr); break; + case HSR_SYSREG_ICC_AP0Rn_EL1(0): case HSR_SYSREG_ICC_AP1Rn_EL1(0): vreg_emulate_apxr0(regs, hsr); break; + case HSR_SYSREG_ICC_AP0Rn_EL1(1): case HSR_SYSREG_ICC_AP1Rn_EL1(1): vreg_emulate_apxr1(regs, hsr); break; + case HSR_SYSREG_ICC_AP0Rn_EL1(2): case HSR_SYSREG_ICC_AP1Rn_EL1(2): vreg_emulate_apxr2(regs, hsr); break; + case HSR_SYSREG_ICC_AP0Rn_EL1(3): case HSR_SYSREG_ICC_AP1Rn_EL1(3): vreg_emulate_apxr3(regs, hsr); break; + case HSR_SYSREG_ICC_HPPIR0_EL1: case HSR_SYSREG_ICC_HPPIR1_EL1: vreg_emulate_hppir1(regs, hsr); break; diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h index 8a4f5b45cb..6d346d84db 100644 --- a/xen/include/asm-arm/arm64/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -97,6 +97,10 @@ #define HSR_SYSREG_ICC_HPPIR1_EL1 HSR_SYSREG(3,0,c12,c12,2) #define HSR_SYSREG_ICC_BPR0_EL1 HSR_SYSREG(3,0,c12,c8,3) #define HSR_SYSREG_ICC_IGRPEN0_EL1 HSR_SYSREG(3,0,c12,c12,6) +#define HSR_SYSREG_ICC_IAR0_EL1 HSR_SYSREG(3,0,c12,c8,0) +#define HSR_SYSREG_ICC_EOIR0_EL1 HSR_SYSREG(3,0,c12,c8,1) +#define HSR_SYSREG_ICC_HPPIR0_EL1 HSR_SYSREG(3,0,c12,c8,2) +#define HSR_SYSREG_ICC_AP0Rn_EL1(n) HSR_SYSREG(3,0,c12,c8,4|n) #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1) #define HSR_SYSREG_PMCR_EL0 HSR_SYSREG(3,3,c9,c12,0) -- 2.14.1 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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