[Xen-devel] [PATCH v2 08/17] arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler

[Manish Jaggi <manish.jaggi@xxxxxxxxxx>]

This patch is a xen port of linux commit
f9e7449c780f688bf61a13dfa8c344afeb4ad6e0
KVM: arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler

Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1
registers. We just map them to the corresponding ICH_AP1Rn_EL2
registers.

This patch calls vreg_emulate_apxrN which has a if (hsr.sysreg.read)
and based on that calls read and write functions. This code placement
is slight different from linux code, which calls read/write functions
from within switch case.

Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx>
---
 xen/arch/arm/arm64/vgic-v3-sr.c     | 76 +++++++++++++++++++++++++++++++++++++
 xen/include/asm-arm/arm64/sysregs.h |  1 +
 2 files changed, 77 insertions(+)

diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index e32ec01f56..c67e7c6ada 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -614,6 +614,66 @@ static void vreg_emulate_eoi(struct cpu_user_regs *regs, 
const union hsr hsr)
     vgic_v3_write_eoir(regs, hsr);
 }
 
+static void vgic_v3_read_apxrn(struct cpu_user_regs *regs,
+                               const union hsr hsr, int n)
+{
+    uint32_t val;
+
+    if ( !vgic_v3_get_group(hsr) )
+        val = vgic_v3_read_ap0rn(n);
+    else
+        val = vgic_v3_read_ap1rn(n);
+
+   set_user_reg(regs, hsr.sysreg.reg, val);
+}
+
+static void vgic_v3_write_apxrn(struct cpu_user_regs *regs,
+                                const union hsr hsr, int n)
+{
+    uint32_t val = get_user_reg(regs, hsr.sysreg.reg);
+
+    if ( !vgic_v3_get_group(hsr) )
+        vgic_v3_write_ap0rn(val, n);
+    else
+        vgic_v3_write_ap1rn(val, n);
+}
+
+static void vreg_emulate_apxr0(struct cpu_user_regs *regs,
+                               const union hsr hsr)
+{
+    if( hsr.sysreg.read )
+        vgic_v3_read_apxrn(regs, hsr, 0);
+    else
+        vgic_v3_write_apxrn(regs, hsr, 0);
+}
+
+static void vreg_emulate_apxr1(struct cpu_user_regs *regs,
+                               const union hsr hsr)
+{
+    if( hsr.sysreg.read )
+        vgic_v3_read_apxrn(regs, hsr, 1);
+    else
+        vgic_v3_write_apxrn(regs, hsr, 1);
+}
+
+static void vreg_emulate_apxr2(struct cpu_user_regs *regs,
+                               const union hsr hsr)
+{
+    if( hsr.sysreg.read )
+        vgic_v3_read_apxrn(regs, hsr, 2);
+    else
+        vgic_v3_write_apxrn(regs, hsr, 2);
+}
+
+static void vreg_emulate_apxr3(struct cpu_user_regs *regs,
+                               const union hsr hsr)
+{
+    if( hsr.sysreg.read )
+        vgic_v3_read_apxrn(regs, hsr, 3);
+    else
+        vgic_v3_write_apxrn(regs, hsr, 3);
+}
+
 /*
  * returns true if the register is emulated.
  */
@@ -648,6 +708,22 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs 
*regs)
         vreg_emulate_eoi(regs, hsr);
         break;
 
+    case HSR_SYSREG_ICC_AP1Rn_EL1(0):
+        vreg_emulate_apxr0(regs, hsr);
+        break;
+
+    case HSR_SYSREG_ICC_AP1Rn_EL1(1):
+        vreg_emulate_apxr1(regs, hsr);
+        break;
+
+    case HSR_SYSREG_ICC_AP1Rn_EL1(2):
+        vreg_emulate_apxr2(regs, hsr);
+        break;
+
+    case HSR_SYSREG_ICC_AP1Rn_EL1(3):
+        vreg_emulate_apxr3(regs, hsr);
+        break;
+
     default:
         ret = false;
         break;
diff --git a/xen/include/asm-arm/arm64/sysregs.h 
b/xen/include/asm-arm/arm64/sysregs.h
index f9110ebf9c..f3cc9ff7b5 100644
--- a/xen/include/asm-arm/arm64/sysregs.h
+++ b/xen/include/asm-arm/arm64/sysregs.h
@@ -85,6 +85,7 @@
 #define HSR_SYSREG_PMINTENCLR_EL1 HSR_SYSREG(3,0,c9,c14,2)
 #define HSR_SYSREG_MAIR_EL1       HSR_SYSREG(3,0,c10,c2,0)
 #define HSR_SYSREG_AMAIR_EL1      HSR_SYSREG(3,0,c10,c3,0)
+#define HSR_SYSREG_ICC_AP1Rn_EL1(n) HSR_SYSREG(3,0,c12,c9, n)
 #define HSR_SYSREG_ICC_SGI1R_EL1  HSR_SYSREG(3,0,c12,c11,5)
 #define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6)
 #define HSR_SYSREG_ICC_SGI0R_EL1  HSR_SYSREG(3,2,c12,c11,7)
-- 
2.14.1


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