Re: [Xen-devel] [PATCH v1 02/15] arm64: Add config for Cavium Thunder erratum 30115

[Julien Grall <julien.grall@xxxxxxx>]

Hi,

On 03/16/2018 11:58 AM, Manish Jaggi wrote:
> Some Cavium Thunder CPUs suffer a problem where a Xen guest may
> inadvertently cause the host kernel to quit receiving interrupts.
> This patch adds CONFIG_CAVIUM_ERRATUM_30115. Subsequent patches will
> provide workaround.
>
> Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx>
>
> diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt
> index c9854c39f4..a2546d4bb5 100644
> --- a/docs/misc/arm/silicon-errata.txt
> +++ b/docs/misc/arm/silicon-errata.txt
> @@ -48,3 +48,4 @@ stable hypervisors.
>   | ARM            | Cortex-A57      | #852523         | N/A                    
>  |
>   | ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075   
>  |
>   | ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220   
>  |
> +| CAVIUM         | ThunderX1       | #30115          | CAVIUM_ERRATUM_30115    
> |
> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> index f58019d6ed..762b761f7d 100644
> --- a/xen/arch/arm/Kconfig
> +++ b/xen/arch/arm/Kconfig
> @@ -169,6 +169,17 @@ config ARM64_ERRATUM_834220
>   
>   	  If unsure, say Y.
>   
> +config CAVIUM_ERRATUM_30115
> +       bool "Cavium Erratum 30115"
> +       depends on HAS_GICV3
> +       help
> +         On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
> +         1.2, and T83 Pass 1.0, guest execution may disable
> +         interrupts in host. Trapping both GICv3 group-0 and group-1
> +         accesses sidesteps the issue.
> +
> +         If unsure, say Y.
> +
>   endmenu
>   
>   source "common/Kconfig"
> diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
> index fe9e9facbe..d49698f785 100644
> --- a/xen/arch/arm/cpuerrata.c
> +++ b/xen/arch/arm/cpuerrata.c
> @@ -56,6 +56,27 @@ static const struct arm_cpu_capabilities arm_errata[] = {
>           MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
>                      (1 << MIDR_VARIANT_SHIFT) | 2),
>       },
> +#endif
> +#ifdef CONFIG_CAVIUM_ERRATUM_30115
> +    {
> +        /* Cavium ThunderX, T88 pass 1.x - 2.2 */
This is quite odd. You specify a number in the commit message here, but 
in the previous one you just say "thunderx1". Can you please try to 
agree on the name? Like the right naming is MIDR_THUNDERX_88.
> +        .desc = "Cavium erratum 30115",
> +        .capability = ARM64_WORKAROUND_CAVIUM_30115,
> +        MIDR_RANGE(MIDR_THUNDERX, 0x00,
> +                   (1 << MIDR_VARIANT_SHIFT) | 2),
> +    },
> +    {
> +        /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
> +        .desc = "Cavium erratum 30115",
> +        .capability = ARM64_WORKAROUND_CAVIUM_30115,
> +        MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02),
> +    },
> +    {
> +        /* Cavium ThunderX, T83 pass 1.0 */
> +        .desc = "Cavium erratum 30115",
> +        .capability = ARM64_WORKAROUND_CAVIUM_30115,
> +        MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00),
> +    },
>   #endif
>       {},
>   };
> diff --git a/xen/include/asm-arm/cpuerrata.h b/xen/include/asm-arm/cpuerrata.h
> index 8b158429c7..521f03521b 100644
> --- a/xen/include/asm-arm/cpuerrata.h
> +++ b/xen/include/asm-arm/cpuerrata.h
> @@ -41,6 +41,7 @@ static inline bool check_workaround_##erratum(void)           
>   \
>   
>   CHECK_WORKAROUND_HELPER(766422, ARM32_WORKAROUND_766422, CONFIG_ARM_32)
>   CHECK_WORKAROUND_HELPER(834220, ARM64_WORKAROUND_834220, CONFIG_ARM_64)
> +CHECK_WORKAROUND_HELPER(30115, ARM64_WORKAROUND_CAVIUM_30115, CONFIG_ARM_64)
Please add cavium_ in the erratum name. So it is easy to know where the 
erratum is from.
>   
>   #undef CHECK_WORKAROUND_HELPER
>   
> diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h
> index f00b6dbd39..d409636bf0 100644
> --- a/xen/include/asm-arm/cpufeature.h
> +++ b/xen/include/asm-arm/cpufeature.h
> @@ -42,8 +42,9 @@
>   #define LIVEPATCH_FEATURE   4
>   #define SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT 5
>   #define SKIP_CTXT_SWITCH_SERROR_SYNC 6
> +#define ARM64_WORKAROUND_CAVIUM_30115 7
>   
> -#define ARM_NCAPS           7
> +#define ARM_NCAPS           8
>   
>   #ifndef __ASSEMBLY__
>   
Cheers,

--
Julien Grall

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