Re: [Xen-devel] [PATCH v2 31/45] ARM: new VGIC: Add SGIR register handler

[Andre Przywara <andre.przywara@xxxxxxxxxx>]

Hi,

On 19/03/18 09:47, Julien Grall wrote:
> Hi Andre,
> 
> On 03/15/2018 08:30 PM, Andre Przywara wrote:
>> Triggering an IPI via this register is v2 specific, so the
>> implementation lives entirely in vgic-mmio-v2.c.
>>
>> This is based on Linux commit 55cc01fb9004, written by Andre Przywara.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@xxxxxxxxxx>
>> ---
>> Changelog v1 ... v2:
>> - remove stray rebase artefact
>>
>>   xen/arch/arm/vgic/vgic-mmio-v2.c | 45
>> +++++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 44 insertions(+), 1 deletion(-)
>>
>> diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c
>> b/xen/arch/arm/vgic/vgic-mmio-v2.c
>> index b333de9ed7..7e17cdc2ad 100644
>> --- a/xen/arch/arm/vgic/vgic-mmio-v2.c
>> +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c
>> @@ -81,6 +81,49 @@ static void vgic_mmio_write_v2_misc(struct vcpu *vcpu,
>>       }
>>   }
>>   +static void vgic_mmio_write_sgir(struct vcpu *source_vcpu,
>> +                                 paddr_t addr, unsigned int len,
>> +                                 unsigned long val)
>> +{
>> +    struct domain *d = source_vcpu->domain;
>> +    unsigned int nr_vcpus = d->max_vcpus;
>> +    unsigned int intid = val & GICD_SGI_INTID_MASK;
>> +    unsigned long targets = (val & GICD_SGI_TARGET_MASK) >>
>> +                            GICD_SGI_TARGET_SHIFT;
>> +    unsigned int vcpu_id;
>> +
>> +    switch ( val & GICD_SGI_TARGET_LIST_MASK )
>> +    {
>> +    case GICD_SGI_TARGET_LIST:                    /* as specified by
>> targets */
>> +        targets &= GENMASK(nr_vcpus, 0);          /* limit to
>> existing VCPUs */
> 
> Shouldn't it be 'nr_vcpus - 1'?

D'oh! Indeed looks like it.
Thanks for catching this!

Cheers,
Andre.

>> +        break;
>> +    case GICD_SGI_TARGET_OTHERS:
>> +        targets = GENMASK(nr_vcpus, 0);           /* all, ...   */
>> +        targets &= ~(1U << source_vcpu->vcpu_id); /*   but self */
>> +        break;
>> +    case GICD_SGI_TARGET_SELF:                    /* this very vCPU
>> only */
>> +        targets = (1U << source_vcpu->vcpu_id);
>> +        break;
>> +    case 0x3:                                     /* reserved */
>> +        return;
>> +    }
> 
> Cheers,
> 

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