[Xen-devel] [PATCH v1 11/15] arm64: vgic-v3: Add ICV_BPR0_EL1 handler

[Manish Jaggi <manish.jaggi@xxxxxxxxxx>]

This patch is ported to xen from linux commit:
423de85a98c2b50715a0784a74f6124fbc0b1548

Add a handler for reading/writing the guest's view of the ICC_BPR0_EL1
register, which is located in the ICH_VMCR_EL2.BPR0 field.

Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx>

diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 537e164062..e79a56619d 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -97,6 +97,41 @@ void handle_bpr1(struct cpu_user_regs *regs, int regidx, 
const union hsr hsr)
         __vgic_v3_write_bpr1(regs, regidx);
 }
 
+static void  __vgic_v3_read_bpr0(struct cpu_user_regs *regs, int regidx)
+{
+    uint32_t vmcr = READ_SYSREG32(ICH_VMCR_EL2);
+    set_user_reg(regs, regidx, __vgic_v3_get_bpr0(vmcr));
+}
+
+static void  __vgic_v3_write_bpr0(struct cpu_user_regs *regs, int regidx)
+{
+    register_t val = get_user_reg(regs, regidx);
+    uint8_t bpr_min = __vgic_v3_bpr_min();
+    uint32_t vmcr = READ_SYSREG32(ICH_VMCR_EL2);
+
+    if ( vmcr & ICH_VMCR_CBPR_MASK )
+        return;
+
+    /* Enforce BPR limiting */
+    if ( val < bpr_min )
+        val = bpr_min;
+
+    val <<= ICH_VMCR_BPR0_SHIFT;
+    val &= ICH_VMCR_BPR0_MASK;
+    vmcr &= ~ICH_VMCR_BPR0_MASK;
+    vmcr |= val;
+
+    WRITE_SYSREG32(vmcr, ICH_VMCR_EL2);
+}
+
+void handle_bpr0(struct cpu_user_regs *regs, int regidx, const union hsr hsr)
+{
+    if ( hsr.sysreg.read )
+        __vgic_v3_read_bpr0(regs, regidx);
+    else
+        __vgic_v3_write_bpr0(regs, regidx);
+}
+
 static void  __vgic_v3_read_igrpen1(struct cpu_user_regs *regs, int regidx)
 {
     uint32_t vmcr = READ_SYSREG32(ICH_VMCR_EL2);
@@ -646,6 +681,10 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs 
*regs, const union hsr hsr
 
     switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
     {
+    case HSR_SYSREG_ICC_BPR0_EL1:
+         handle_bpr0(regs, regidx, hsr);
+         break;
+
     case HSR_SYSREG_ICC_BPR1_EL1:
          handle_bpr1(regs, regidx, hsr);
          break;
diff --git a/xen/include/asm-arm/arm64/sysregs.h 
b/xen/include/asm-arm/arm64/sysregs.h
index c23c4a33b2..ef01576b01 100644
--- a/xen/include/asm-arm/arm64/sysregs.h
+++ b/xen/include/asm-arm/arm64/sysregs.h
@@ -94,6 +94,7 @@
 #define HSR_SYSREG_ICC_IAR1_EL1   HSR_SYSREG(3,0,c12,c12,0)
 #define HSR_SYSREG_ICC_EOIR1_EL1  HSR_SYSREG(3,0,c12,c12,1)
 #define HSR_SYSREG_ICC_HPPIR1_EL1 HSR_SYSREG(3,0,c12,c12,2)
+#define HSR_SYSREG_ICC_BPR0_EL1          HSR_SYSREG(3,0,c12,c8,3)
 #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
 
 #define HSR_SYSREG_PMCR_EL0       HSR_SYSREG(3,3,c9,c12,0)
-- 
2.14.1


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