Re: [Xen-devel] [PATCH] x86: vlapic: Clear vector's TMR bit upon acceptance of edge-triggered interrupt to IRR

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 15.03.18 at 00:35, <liran.alon@xxxxxxxxxx> wrote:
> According to Intel SDM 10.8.4 Interrupt Acceptance for Fixed Interrupts:
> "The trigger mode register (TMR) indicates the trigger mode of the
> interrupt (see Figure 10-20). Upon acceptance of an interrupt
> into the IRR, the corresponding TMR bit is cleared for
> edge-triggered interrupts and set for level-triggered interrupts.
> If a TMR bit is set when an EOI cycle for its corresponding
> interrupt vector is generated, an EOI message is sent to
> all I/O APICs."
> 
> Before this patch TMR-bit was cleared on LAPIC EOI which is not what
> real hardware does. This was also confirmed in KVM upstream commit
> a0c9a822bf37 ("KVM: dont clear TMR on EOI").
> 
> Behavior after this patch is aligned with both Intel SDM and KVM
> implementation.
> 
> Signed-off-by: Liran Alon <liran.alon@xxxxxxxxxx>
> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>
> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>

Boris - which of the two tags is the correct one?

Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>

Jan


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