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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v2 9/7] x86/XPTI: reduce .text.entry
This exposes less code pieces and at the same time reduces the range
covered from slightly above 3 pages to a little below 2 of them.
The code being moved is entirely unchanged, except for the removal of
trailing blanks and a pointless q suffix from "retq".
A few more small pieces could be moved, but it seems better to me to
leave them where they are to not make it overly hard to follow code
paths.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
--- a/xen/arch/x86/x86_64/compat/entry.S
+++ b/xen/arch/x86/x86_64/compat/entry.S
@@ -13,8 +13,6 @@
#include <public/xen.h>
#include <irq_vectors.h>
- .section .text.entry, "ax", @progbits
-
ENTRY(entry_int82)
ASM_CLAC
pushq $0
@@ -199,6 +197,8 @@ ENTRY(compat_post_handle_exception)
movb $0,TRAPBOUNCE_flags(%rdx)
jmp compat_test_all_events
+ .section .text.entry, "ax", @progbits
+
/* See lstar_enter for entry register state. */
ENTRY(cstar_enter)
ALTERNATIVE nop, sti, X86_FEATURE_NO_XPTI
@@ -256,6 +256,8 @@ UNLIKELY_END(compat_syscall_gpf)
movb %cl,TRAPBOUNCE_flags(%rdx)
jmp .Lcompat_bounce_exception
+ .text
+
ENTRY(compat_sysenter)
CR4_PV32_RESTORE
movq VCPU_trap_ctxt(%rbx),%rcx
@@ -275,9 +277,6 @@ ENTRY(compat_int80_direct_trap)
call compat_create_bounce_frame
jmp compat_test_all_events
- /* compat_create_bounce_frame & helpers don't need to be in
.text.entry */
- .text
-
/* CREATE A BASIC EXCEPTION FRAME ON GUEST OS (RING-1) STACK: */
/* {[ERRCODE,] EIP, CS, EFLAGS, [ESP, SS]} */
/* %rdx: trap_bounce, %rbx: struct vcpu */
--- a/xen/arch/x86/x86_64/entry.S
+++ b/xen/arch/x86/x86_64/entry.S
@@ -14,8 +14,6 @@
#include <public/xen.h>
#include <irq_vectors.h>
- .section .text.entry, "ax", @progbits
-
/* %rbx: struct vcpu */
ENTRY(switch_to_kernel)
leaq VCPU_trap_bounce(%rbx),%rdx
@@ -34,8 +32,107 @@ ENTRY(switch_to_kernel)
movb %cl,TRAPBOUNCE_flags(%rdx)
call create_bounce_frame
andl $~X86_EFLAGS_DF,UREGS_eflags(%rsp)
+/* %rbx: struct vcpu */
+test_all_events:
+ ASSERT_NOT_IN_ATOMIC
+ cli # tests must not race interrupts
+/*test_softirqs:*/
+ movl VCPU_processor(%rbx),%eax
+ shll $IRQSTAT_shift,%eax
+ leaq irq_stat+IRQSTAT_softirq_pending(%rip),%rcx
+ cmpl $0,(%rcx,%rax,1)
+ jne process_softirqs
+ testb $1,VCPU_mce_pending(%rbx)
+ jnz process_mce
+.Ltest_guest_nmi:
+ testb $1,VCPU_nmi_pending(%rbx)
+ jnz process_nmi
+test_guest_events:
+ movq VCPU_vcpu_info(%rbx),%rax
+ movzwl VCPUINFO_upcall_pending(%rax),%eax
+ decl %eax
+ cmpl $0xfe,%eax
+ ja restore_all_guest
+/*process_guest_events:*/
+ sti
+ leaq VCPU_trap_bounce(%rbx),%rdx
+ movq VCPU_event_addr(%rbx),%rax
+ movq %rax,TRAPBOUNCE_eip(%rdx)
+ movb $TBF_INTERRUPT,TRAPBOUNCE_flags(%rdx)
+ call create_bounce_frame
jmp test_all_events
+ ALIGN
+/* %rbx: struct vcpu */
+process_softirqs:
+ sti
+ call do_softirq
+ jmp test_all_events
+
+ ALIGN
+/* %rbx: struct vcpu */
+process_mce:
+ testb $1 << VCPU_TRAP_MCE,VCPU_async_exception_mask(%rbx)
+ jnz .Ltest_guest_nmi
+ sti
+ movb $0,VCPU_mce_pending(%rbx)
+ call set_guest_machinecheck_trapbounce
+ test %eax,%eax
+ jz test_all_events
+ movzbl VCPU_async_exception_mask(%rbx),%edx # save mask for the
+ movb %dl,VCPU_mce_old_mask(%rbx) # iret hypercall
+ orl $1 << VCPU_TRAP_MCE,%edx
+ movb %dl,VCPU_async_exception_mask(%rbx)
+ jmp process_trap
+
+ ALIGN
+/* %rbx: struct vcpu */
+process_nmi:
+ testb $1 << VCPU_TRAP_NMI,VCPU_async_exception_mask(%rbx)
+ jnz test_guest_events
+ sti
+ movb $0,VCPU_nmi_pending(%rbx)
+ call set_guest_nmi_trapbounce
+ test %eax,%eax
+ jz test_all_events
+ movzbl VCPU_async_exception_mask(%rbx),%edx # save mask for the
+ movb %dl,VCPU_nmi_old_mask(%rbx) # iret hypercall
+ orl $1 << VCPU_TRAP_NMI,%edx
+ movb %dl,VCPU_async_exception_mask(%rbx)
+ /* FALLTHROUGH */
+process_trap:
+ leaq VCPU_trap_bounce(%rbx),%rdx
+ call create_bounce_frame
+ jmp test_all_events
+
+/* No special register assumptions. */
+ENTRY(ret_from_intr)
+ GET_CURRENT(bx)
+ testb $3,UREGS_cs(%rsp)
+ jz restore_all_xen
+ movq VCPU_domain(%rbx),%rax
+ testb $1,DOMAIN_is_32bit_pv(%rax)
+ jz test_all_events
+ jmp compat_test_all_events
+
+/* Enable NMIs. No special register assumptions. Only %rax is not preserved.
*/
+ENTRY(enable_nmis)
+ movq %rsp, %rax /* Grab RSP before pushing */
+
+ /* Set up stack frame */
+ pushq $0 /* SS */
+ pushq %rax /* RSP */
+ pushfq /* RFLAGS */
+ pushq $__HYPERVISOR_CS /* CS */
+ leaq 1f(%rip),%rax
+ pushq %rax /* RIP */
+
+ iretq /* Disable the hardware NMI latch */
+1:
+ ret
+
+ .section .text.entry, "ax", @progbits
+
/* %rbx: struct vcpu, interrupts disabled */
restore_all_guest:
ASSERT_INTERRUPTS_DISABLED
@@ -197,80 +294,8 @@ ENTRY(lstar_enter)
mov %rsp, %rdi
call pv_hypercall
-
-/* %rbx: struct vcpu */
-test_all_events:
- ASSERT_NOT_IN_ATOMIC
- cli # tests must not race interrupts
-/*test_softirqs:*/
- movl VCPU_processor(%rbx),%eax
- shll $IRQSTAT_shift,%eax
- leaq irq_stat+IRQSTAT_softirq_pending(%rip),%rcx
- cmpl $0,(%rcx,%rax,1)
- jne process_softirqs
- testb $1,VCPU_mce_pending(%rbx)
- jnz process_mce
-.Ltest_guest_nmi:
- testb $1,VCPU_nmi_pending(%rbx)
- jnz process_nmi
-test_guest_events:
- movq VCPU_vcpu_info(%rbx),%rax
- movzwl VCPUINFO_upcall_pending(%rax),%eax
- decl %eax
- cmpl $0xfe,%eax
- ja restore_all_guest
-/*process_guest_events:*/
- sti
- leaq VCPU_trap_bounce(%rbx),%rdx
- movq VCPU_event_addr(%rbx),%rax
- movq %rax,TRAPBOUNCE_eip(%rdx)
- movb $TBF_INTERRUPT,TRAPBOUNCE_flags(%rdx)
- call create_bounce_frame
jmp test_all_events
- ALIGN
-/* %rbx: struct vcpu */
-process_softirqs:
- sti
- call do_softirq
- jmp test_all_events
-
- ALIGN
-/* %rbx: struct vcpu */
-process_mce:
- testb $1 << VCPU_TRAP_MCE,VCPU_async_exception_mask(%rbx)
- jnz .Ltest_guest_nmi
- sti
- movb $0,VCPU_mce_pending(%rbx)
- call set_guest_machinecheck_trapbounce
- test %eax,%eax
- jz test_all_events
- movzbl VCPU_async_exception_mask(%rbx),%edx # save mask for the
- movb %dl,VCPU_mce_old_mask(%rbx) # iret hypercall
- orl $1 << VCPU_TRAP_MCE,%edx
- movb %dl,VCPU_async_exception_mask(%rbx)
- jmp process_trap
-
- ALIGN
-/* %rbx: struct vcpu */
-process_nmi:
- testb $1 << VCPU_TRAP_NMI,VCPU_async_exception_mask(%rbx)
- jnz test_guest_events
- sti
- movb $0,VCPU_nmi_pending(%rbx)
- call set_guest_nmi_trapbounce
- test %eax,%eax
- jz test_all_events
- movzbl VCPU_async_exception_mask(%rbx),%edx # save mask for the
- movb %dl,VCPU_nmi_old_mask(%rbx) # iret hypercall
- orl $1 << VCPU_TRAP_NMI,%edx
- movb %dl,VCPU_async_exception_mask(%rbx)
- /* FALLTHROUGH */
-process_trap:
- leaq VCPU_trap_bounce(%rbx),%rdx
- call create_bounce_frame
- jmp test_all_events
-
ENTRY(sysenter_entry)
ALTERNATIVE nop, sti, X86_FEATURE_NO_XPTI
pushq $FLAT_USER_SS
@@ -554,16 +579,6 @@ ENTRY(common_interrupt)
ALTERNATIVE_NOP .Lintr_cr3_restore, .Lintr_cr3_end, X86_FEATURE_NO_XPTI
ALTERNATIVE_NOP .Lintr_cr3_start, .Lintr_cr3_okay, X86_FEATURE_NO_XPTI
-/* No special register assumptions. */
-ENTRY(ret_from_intr)
- GET_CURRENT(bx)
- testb $3,UREGS_cs(%rsp)
- jz restore_all_xen
- movq VCPU_domain(%rbx),%rax
- testb $1,DOMAIN_is_32bit_pv(%rax)
- jz test_all_events
- jmp compat_test_all_events
-
ENTRY(page_fault)
movl $TRAP_page_fault,4(%rsp)
/* No special register assumptions. */
@@ -878,22 +893,6 @@ ENTRY(machine_check)
movl $TRAP_machine_check,4(%rsp)
jmp handle_ist_exception
-/* Enable NMIs. No special register assumptions. Only %rax is not preserved.
*/
-ENTRY(enable_nmis)
- movq %rsp, %rax /* Grab RSP before pushing */
-
- /* Set up stack frame */
- pushq $0 /* SS */
- pushq %rax /* RSP */
- pushfq /* RFLAGS */
- pushq $__HYPERVISOR_CS /* CS */
- leaq 1f(%rip),%rax
- pushq %rax /* RIP */
-
- iretq /* Disable the hardware NMI latch */
-1:
- retq
-
/* No op trap handler. Required for kexec crash path. */
GLOBAL(trap_nop)
iretq
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