Re: [Xen-devel] [PATCH v4 0/7] unsafe big.LITTLE support

[Peng Fan <van.freenix@xxxxxxxxx>]

Hi Stefano,
On Fri, Mar 02, 2018 at 11:05:54AM -0800, Stefano Stabellini wrote:
>Hi all,
>
>This series changes the initialization of two virtual registers to make
>sure they match the value of the underlying physical cpu.
>
>It also disables cpus different from the boot cpu, unless a newly
>introduced command line option is specified. In that case, it explains
>how to setup the system to avoid corruptions, which involves manually
>specifying the cpu affinity of all domains, because the scheduler still
>lacks big.LITTLE support.
>
>In the uncommon case of a system where the cacheline sizes are different
>across cores, it disables all cores that have a different dcache line size
>from the boot cpu. In fact, it is not sufficient to use the dcache line
>size of the current cpu, it would be necessary to use the minimum across
>all dcache line sizes of all cores.  Given that it is actually uncommon
>even in big.LITTLE systems, just disable cpus for now.
>
>The first patch in the series is a fix for the way we read the dcache
>line size.

I am trying the patchset, but I meet issue that Guest Big/Little with
vcpu not working properly. As my current hardware has an issue
which has fix in Kernel, 
https://source.codeaurora.org/external/imx/linux-imx/commit/?h=imx_4.9.51_imx8_beta2&id=917cc3a8db2f3609ef8e2f59e7bcd31aa2cd4e59

I am not sure whether this issue cause DomU big/Little not work.
So wonder has this patchset been tested on Big/Little Hardware?

Thanks,
Peng.

>
>Cheers,
>
>Stefano
>
>
>Julien Grall (1):
>      xen/arm: Park CPUs with a MIDR different from the boot CPU.
>
>Stefano Stabellini (6):
>      xen/arm: Read the dcache line size from CTR register
>      xen/arm: make processor a per cpu variable
>      xen/arm: read ACTLR on the pcpu where the vcpu will run
>      xen/arm: set VPIDR based on the MIDR value of the underlying pCPU
>      xen/arm: update the docs about heterogeneous computing
>      xen/arm: disable CPUs with different dcache line sizes
>
> docs/misc/arm/big.LITTLE.txt        | 46 +++++++++++++++++++++++++++++++++++++
> docs/misc/xen-command-line.markdown | 15 ++++++++++++
> xen/arch/arm/arm32/head.S           |  2 +-
> xen/arch/arm/arm64/head.S           |  2 +-
> xen/arch/arm/domain.c               | 15 ++++++------
> xen/arch/arm/processor.c            |  8 +++----
> xen/arch/arm/setup.c                | 17 ++------------
> xen/arch/arm/smpboot.c              | 39 +++++++++++++++++++++++++++++++
> xen/arch/arm/vcpreg.c               |  4 ++--
> xen/include/asm-arm/cpregs.h        |  2 ++
> xen/include/asm-arm/domain.h        |  3 ---
> xen/include/asm-arm/page.h          | 27 +++++++++++++++-------
> 12 files changed, 138 insertions(+), 42 deletions(-)
> create mode 100644 docs/misc/arm/big.LITTLE.txt
>
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