[Xen-devel] [PATCH RFC 21/44] x86/smp: Switch to using the percpu IDT mappings

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

The loading of IDTR is moved out of load_system_tables() and into
early_switch_to_idle().

One complication for the BSP is that IST references still need to remain
uninitalised until reinit_bsp_stack().  Therefore, early_switch_to_idle() is
extended to take a bsp boolean.

For VT-x guests, HOST_IDTR_BASE needs altering, so a #VMExit doesn't change
the mappings we use.  As this is now a compile-time constant, it moves from
vmx_set_host_env() to construct_vmcs() to avoid rewriting it on every context
switch.

Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 xen/arch/x86/cpu/common.c    |  8 --------
 xen/arch/x86/hvm/vmx/vmcs.c  |  4 +++-
 xen/arch/x86/setup.c         | 24 ++++++++++++++++++++++--
 xen/arch/x86/smpboot.c       |  2 +-
 xen/include/asm-x86/system.h |  2 +-
 5 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index b18e0f4..14743b6 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -644,7 +644,6 @@ void __init early_cpu_init(void)
  */
 void load_system_tables(void)
 {
-       unsigned int cpu = smp_processor_id();
        unsigned long stack_bottom = get_stack_bottom(),
                stack_top = stack_bottom & ~(STACK_SIZE - 1);
 
@@ -658,10 +657,6 @@ void load_system_tables(void)
                .base = (unsigned long)gdt,
                .limit = LAST_RESERVED_GDT_BYTE,
        };
-       const struct desc_ptr idtr = {
-               .base = (unsigned long)idt_tables[cpu],
-               .limit = (IDT_ENTRIES * sizeof(idt_entry_t)) - 1,
-       };
 
        *tss = (struct tss_struct){
                /* Main stack for interrupts/exceptions. */
@@ -699,12 +694,9 @@ void load_system_tables(void)
                SYS_DESC_tss_busy);
 
        lgdt(&gdtr);
-       lidt(&idtr);
        ltr(TSS_ENTRY << 3);
        lldt(0);
 
-       enable_each_ist(idt_tables[cpu]);
-
        /*
         * Bottom-of-stack must be 16-byte aligned!
         *
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index e7818ca..f99f1bb 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -804,7 +804,6 @@ static void vmx_set_host_env(struct vcpu *v)
 
     __vmwrite(HOST_GDTR_BASE,
               (unsigned long)(this_cpu(gdt_table) - FIRST_RESERVED_GDT_ENTRY));
-    __vmwrite(HOST_IDTR_BASE, (unsigned long)idt_tables[cpu]);
 
     __vmwrite(HOST_TR_BASE, (unsigned long)&per_cpu(init_tss, cpu));
 
@@ -1133,6 +1132,9 @@ static int construct_vmcs(struct vcpu *v)
     /* Disable PML anyway here as it will only be enabled in log dirty mode */
     v->arch.hvm_vmx.secondary_exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
 
+    /* Host system tables. */
+    __vmwrite(HOST_IDTR_BASE, PERCPU_IDT_MAPPING);
+
     /* Host data selectors. */
     __vmwrite(HOST_SS_SELECTOR, __HYPERVISOR_DS);
     __vmwrite(HOST_DS_SELECTOR, __HYPERVISOR_DS);
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 5fa70bd..662c383 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -237,12 +237,25 @@ void __init discard_initial_images(void)
 
 extern char __init_begin[], __init_end[], __bss_start[], __bss_end[];
 
-void early_switch_to_idle(void)
+void early_switch_to_idle(bool bsp)
 {
     unsigned int cpu = smp_processor_id();
     struct vcpu *v = idle_vcpu[cpu];
     unsigned long cr4 = read_cr4();
 
+    /*
+     * VT-x hardwires the IDT limit at 0xffff on VMExit.
+     *
+     * We don't wish to reload on vcpu context switch, so have arranged for
+     * nothing else to live within 64k of the base.  Unilaterally setting the
+     * limit to 0xffff avoids leaking whether HVM vcpus are running to PV
+     * guests via SIDT.
+     */
+    const struct desc_ptr idtr = {
+        .base = PERCPU_IDT_MAPPING,
+        .limit = 0xffff,
+    };
+
     set_current(v);
     per_cpu(curr_vcpu, cpu) = v;
 
@@ -257,12 +270,17 @@ void early_switch_to_idle(void)
                    : "memory" );
 
     per_cpu(curr_ptbase, cpu) = v->arch.cr3;
+
+    lidt(&idtr);
+
+    if ( likely(!bsp) ) /* BSP IST setup deferred. */
+        enable_each_ist(idt_tables[cpu]);
 }
 
 static void __init init_idle_domain(void)
 {
     scheduler_init();
-    early_switch_to_idle();
+    early_switch_to_idle(true);
 }
 
 void srat_detect_node(int cpu)
@@ -631,6 +649,8 @@ static void __init noreturn reinit_bsp_stack(void)
     /* Update TSS and ISTs */
     load_system_tables();
 
+    enable_each_ist(idt_tables[0]);
+
     /* Update SYSCALL trampolines */
     percpu_traps_init();
 
diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
index 4df7775..7f02dd8 100644
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -311,7 +311,7 @@ void start_secondary(void *unused)
     set_processor_id(cpu);
     get_cpu_info()->cr4 = XEN_MINIMAL_CR4;
 
-    early_switch_to_idle();
+    early_switch_to_idle(false);
 
     rdmsrl(MSR_EFER, this_cpu(efer));
 
diff --git a/xen/include/asm-x86/system.h b/xen/include/asm-x86/system.h
index ee57631..5cf8827 100644
--- a/xen/include/asm-x86/system.h
+++ b/xen/include/asm-x86/system.h
@@ -230,7 +230,7 @@ static inline int local_irq_is_enabled(void)
 
 void trap_init(void);
 void init_idt_traps(void);
-void early_switch_to_idle(void);
+void early_switch_to_idle(bool bsp);
 void load_system_tables(void);
 void percpu_traps_init(void);
 void subarch_percpu_traps_init(void);
-- 
2.1.4


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