Re: [Xen-devel] [PATCH v4 04/15] x86: implement data structure and CPU init flow for MBA

["Jan Beulich" <jbeulich@xxxxxxxx>]

>>> Yi Sun <yi.y.sun@xxxxxxxxxxxxxxx> 09/29/17 3:55 AM >>>
>On 17-09-28 05:00:09, Jan Beulich wrote:
>> >>> On 23.09.17 at 11:48, <yi.y.sun@xxxxxxxxxxxxxxx> wrote:
>> > One thrtl register of MBA stores a throttle value for one or more
>> > domains. The throttle value means the delay between L2 cache and next
>> > cache level.
>> 
>> What is a delay between two cache levels?
>> 
>There is a "programmable rate controller" between them to indirectly control
>the bandwidth.

I'm afraid I don't feel like this answers my question. Anyway - the sentence
needs some re-phrasing so it becomes clear what you're talking about.

>> > @@ -1410,6 +1496,7 @@ static void psr_cpu_init(void)
>> >      unsigned int socket, cpu = smp_processor_id();
>> >      struct feat_node *feat;
>> >      struct cpuid_leaf regs;
>> > +    uint32_t ebx;
>> 
>> Is this local variable really a big help? To me it looks like it only
>> makes the patch larger without actually improving anything,
>> and without being related to the subject of the patch.
>> 
>IMHO, it can avoid the 'cpuid_count_leaf()' being repeatedly called. Without 
>it,
>we have to call 'cpuid_count_leaf()' for 2 more times.

Hmm, didn't you simply replace regs.b uses with ebx? Or did I overlook a place
where regs is being overwritten before the last of these regs.b uses (in which 
case
I think your change is fine)?

Jan


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