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Re: [Xen-devel] [PATCH 26/27 v8] xen/arm: vpl011: Correct the logic for asserting/de-asserting SBSA UART TX interrupt

Hi Bhupinder,

I am just commenting on the commit message, Andre already commented the code.

On 28/08/17 09:56, Bhupinder Thakur wrote:
This patch fixes the issue observed when pl011 patches were tested on
the junos hardware by Andre/Julien. It was observed that when large output is
generated such as on running 'find /', output was getting truncated 
due to OUT ring buffer getting full.

This issue was due to the fact that the SBSA UART driver expects that when
a TX interrupt is asserted then the FIFO queue should be atleast half empty and
that it can write N bytes in the FIFO, where N is half the FIFO queue size, 
the bytes getting dropped due to FIFO getting full.

This requirement is as per section 3.4.2 of [1], which is:


This register does not exist in the SBSA, so you cannot say it is a requirement from the specification. The emulation should be based on the specification and not how a driver behave. You don't know how other OS have implemented the driver.

As I mentioned in my previous answer, we are in process to clarify in the specification and we can currently assume the interrupt will be triggered at halfway.

So the commit message should reflect that.


Julien Grall

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