Re: [Xen-devel] [PATCH 11/27] xen/arm: Add FnV field in hsr_*abt

[Andre Przywara <andre.przywara@xxxxxxx>]

Hi,

On 14/08/17 15:24, Julien Grall wrote:
> FnV (FAR not Valid) bit was introduced by ARMv8 in both AArch32 and
> AArch64 (See D7-2275, D7-2277, G6-4958, G6-4962 in ARM DDI 0487B.a).

I understand that this just prepares the data structures for patch #14,
but I was wondering if we should update the other fields on the way as
well, for instance there is now "ar" in Aarch32 also.

> Signed-off-by: Julien Grall <julien.grall@xxxxxxx>

But the actual bits are correct, so if we just need "fnv", then this is:

Reviewed-by: Andre Przywara <andre.przywara@xxxxxxx>

> ---
>  xen/include/asm-arm/processor.h | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index 51645f08c0..3ef606c554 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -509,7 +509,8 @@ union hsr {
>          unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */
>          unsigned long res1:1;  /* RES0 */
>          unsigned long eat:1;   /* External abort type */
> -        unsigned long res2:15;
> +        unsigned long fnv:1;   /* FAR not Valid */
> +        unsigned long res2:14;
>          unsigned long len:1;   /* Instruction length */
>          unsigned long ec:6;    /* Exception Class */
>      } iabt; /* HSR_EC_INSTR_ABORT_* */
> @@ -520,10 +521,11 @@ union hsr {
>          unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */
>          unsigned long cache:1; /* Cache Maintenance */
>          unsigned long eat:1;   /* External Abort Type */
> +        unsigned long fnv:1;   /* FAR not Valid */
>  #ifdef CONFIG_ARM_32
> -        unsigned long sbzp0:6;
> +        unsigned long sbzp0:5;

This can be broken down further, as the ARMv8 ARM explains more of these
bits now. "ar" is now also defined here, for instance.

>  #else
> -        unsigned long sbzp0:4;
> -        unsigned long sbzp0:3;

And also on the Aarch64 side there are now more bits used.

Cheers,
Andre.

>          unsigned long ar:1;    /* Acquire Release */
>          unsigned long sf:1;    /* Sixty Four bit register */
>  #endif
> 

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