[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Xen-devel] [RFC PATCH v2 16/22] ARM: vITS: rename lpi_vcpu_id to vcpu_id



Since we will soon store a virtual IRQ's target VCPU in struct pending_irq,
generalise the existing storage for an LPI's target to cover all IRQs.
This just renames "lpi_vcpu_id" to "vcpu_id", but doesn't change anything
else yet.

Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
---
 xen/arch/arm/gic-v3-lpi.c  | 2 +-
 xen/arch/arm/vgic-v3-its.c | 7 +++----
 xen/arch/arm/vgic.c        | 6 +++---
 xen/include/asm-arm/vgic.h | 2 +-
 4 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c
index c3474f5..2306b58 100644
--- a/xen/arch/arm/gic-v3-lpi.c
+++ b/xen/arch/arm/gic-v3-lpi.c
@@ -149,7 +149,7 @@ void vgic_vcpu_inject_lpi(struct domain *d, unsigned int 
virq)
     if ( !p )
         return;
 
-    vcpu_id = ACCESS_ONCE(p->lpi_vcpu_id);
+    vcpu_id = ACCESS_ONCE(p->vcpu_id);
     if ( vcpu_id >= d->max_vcpus )
           return;
 
diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
index 705708a..682ce10 100644
--- a/xen/arch/arm/vgic-v3-its.c
+++ b/xen/arch/arm/vgic-v3-its.c
@@ -560,7 +560,7 @@ static int its_handle_invall(struct virt_its *its, uint64_t 
*cmdptr)
         {
             vgic_irq_lock(pirqs[i], flags);
             /* We only care about LPIs on our VCPU. */
-            if ( pirqs[i]->lpi_vcpu_id != vcpu->vcpu_id )
+            if ( pirqs[i]->vcpu_id != vcpu->vcpu_id )
             {
                 vgic_irq_unlock(pirqs[i], flags);
                 continue;
@@ -781,7 +781,7 @@ static int its_handle_mapti(struct virt_its *its, uint64_t 
*cmdptr)
     if ( ret )
         goto out_remove_host_entry;
 
-    pirq->lpi_vcpu_id = vcpu->vcpu_id;
+    pirq->vcpu_id = vcpu->vcpu_id;
     /*
      * Mark this LPI as new, so any older (now unmapped) LPI in any LR
      * can be easily recognised as such.
@@ -852,8 +852,7 @@ static int its_handle_movi(struct virt_its *its, uint64_t 
*cmdptr)
      */
     spin_lock_irqsave(&ovcpu->arch.vgic.lock, flags);
 
-    /* Update our cached vcpu_id in the pending_irq. */
-    p->lpi_vcpu_id = nvcpu->vcpu_id;
+    p->vcpu_id = nvcpu->vcpu_id;
 
     spin_unlock_irqrestore(&ovcpu->arch.vgic.lock, flags);
 
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 6722924..1ba0010 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -63,15 +63,15 @@ struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, 
unsigned int irq)
 
 void vgic_init_pending_irq(struct pending_irq *p, unsigned int virq)
 {
-    /* The lpi_vcpu_id field must be big enough to hold a VCPU ID. */
-    BUILD_BUG_ON(BIT(sizeof(p->lpi_vcpu_id) * 8) < MAX_VIRT_CPUS);
+    /* The vcpu_id field must be big enough to hold a VCPU ID. */
+    BUILD_BUG_ON(BIT(sizeof(p->vcpu_id) * 8) < MAX_VIRT_CPUS);
 
     memset(p, 0, sizeof(*p));
     INIT_LIST_HEAD(&p->inflight);
     INIT_LIST_HEAD(&p->lr_queue);
     spin_lock_init(&p->lock);
     p->irq = virq;
-    p->lpi_vcpu_id = INVALID_VCPU_ID;
+    p->vcpu_id = INVALID_VCPU_ID;
 }
 
 static void vgic_rank_init(struct vgic_irq_rank *rank, uint8_t index,
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 7c6067d..ffd9a95 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -81,7 +81,7 @@ struct pending_irq
     uint8_t lr;
     uint8_t cur_priority;       /* Holds the priority of an injected IRQ. */
     uint8_t priority;           /* Holds the priority for any new IRQ. */
-    uint8_t lpi_vcpu_id;        /* The VCPU for an LPI. */
+    uint8_t vcpu_id;            /* The VCPU target for any new IRQ. */
     /* inflight is used to append instances of pending_irq to
      * vgic.inflight_irqs */
     struct list_head inflight;
-- 
2.9.0


_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxx
https://lists.xen.org/xen-devel

 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.