 
	
| [Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH] x86emul: correct EVEX register extension bit handling for non-64-bit modes
 While these are latent issues only for now, correct them right away:
- EVEX.V' (called RX in our code) needs to uniformly be 1,
- EXEX.R' (called R in our code) is uniformly being ignored.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -2544,6 +2544,12 @@ x86_decode(
                         evex.raw[1] = vex.raw[1];
                         evex.raw[2] = insn_fetch_type(uint8_t);
 
+                        if ( !mode_64bit() )
+                        {
+                            generate_exception_if(!evex.RX, EXC_UD);
+                            evex.R = 1;
+                        }
+
                         vex.opcx = evex.opcx;
                         break;
                     case 0xc4:
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