Re: [Xen-devel] [PATCH v11 13/23] x86: refactor psr: CDP: implement CPU init flow.

[Yi Sun <yi.y.sun@xxxxxxxxxxxxxxx>]

On 17-06-06 02:38:27, Jan Beulich wrote:
> >>> On 06.06.17 at 10:13, <yi.y.sun@xxxxxxxxxxxxxxx> wrote:
> > On 17-06-06 01:45:11, Jan Beulich wrote:
> >> >>> On 02.06.17 at 09:26, <yi.y.sun@xxxxxxxxxxxxxxx> wrote:
> >> > On 17-05-31 03:37:48, Jan Beulich wrote:
> >> >> >>> On 03.05.17 at 10:44, <yi.y.sun@xxxxxxxxxxxxxxx> wrote:
> >> >> > +        /* Cut half of cos_max when CDP is enabled. */
> >> >> > +        feat->cos_max >>= 1;
> >> >> > +
> >> >> > +        /* We only write mask1 since mask0 is always all ones by 
> >> >> > default. */
> >> >> 
> >> >> Is this, btw, just reset state or even guaranteed after offlining
> >> >> and re-onlining a CPU?
> >> >> 
> >> > Below MSRs are all per socket. So, we just need reset them when socket is
> >> > online.
> >> 
> >> Which I hope you've understood then means the comment and
> >> presumably also the code here need further refinement.
> >> 
> > Spec states it below. So, the mask0 is guranteed.
> > "the default mask in IA32_L3_MASK_0 - which is all “1”s (on reset)"
> 
> Sigh. I did ask very clearly (and this is still visible above) about
> the case where the CPU did _not_ undergo a reset cycle.
> 
Sorry, I think I must mis-understand your question. SW never modifies value
of COS ID 0 mask register. So, the value in mask0 will not be changed after
socket first online (mask0 is set to default by HW this time). So, we think
it is not necessary to restore mask0 value to default here.

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