[Xen-devel] [ovmf baseline-only test] 71406: tolerable FAIL

[Platform Team regression test user <citrix-osstest@xxxxxxxxxxxxxx>]

This run is configured for baseline tests only.

flight 71406 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/71406/

Failures :-/ but no regressions.

Regressions which are regarded as allowable (not blocking):
 build-amd64-libvirt           5 libvirt-build                fail   like 71392
 build-i386-libvirt            5 libvirt-build                fail   like 71392

version targeted for testing:
 ovmf                 0e07733023ea26901eec5c51d17e8f38d10d0dea
baseline version:
 ovmf                 7320b8ed1879b31657a8d6a62e6cd0ff1f645754

Last test of basis    71392  2017-05-22 12:17:07 Z    0 days
Testing same since    71406  2017-05-22 22:20:19 Z    0 days    1 attempts

------------------------------------------------------------
People who touched revisions under test:
  Evan Lloyd <evan.lloyd@xxxxxxx>
  Sami Mujawar <sami.mujawar@xxxxxxx>

jobs:
 build-amd64-xsm                                              pass    
 build-i386-xsm                                               pass    
 build-amd64                                                  pass    
 build-i386                                                   pass    
 build-amd64-libvirt                                          fail    
 build-i386-libvirt                                           fail    
 build-amd64-pvops                                            pass    
 build-i386-pvops                                             pass    
 test-amd64-amd64-xl-qemuu-ovmf-amd64                         pass    
 test-amd64-i386-xl-qemuu-ovmf-amd64                          pass    


------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images

Logs, config files, etc. are available at
    http://osstest.xs.citrite.net/~osstest/testlogs/logs

Test harness code can be found at
    http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Push not applicable.

------------------------------------------------------------
commit 0e07733023ea26901eec5c51d17e8f38d10d0dea
Author: Sami Mujawar <sami.mujawar@xxxxxxx>
Date:   Tue May 16 11:10:45 2017 +0100

    ArmPlatformPkg: Timer access for non-secure EL1/0
    
    According to Section 2.3.6 of the "UEFI Specification 2.6 Errata A";
    the primary CPU must be configured such that 'Timer access must be
    provided to non-secure EL1 and EL0 by setting bits EL1PCTEN and
    EL1PCEN in register CNTHCTL_EL2.'
    
    This commit adds this missing set-up to the PrePi and PrePeiCore
    modules.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Sami Mujawar <sami.mujawar@xxxxxxx>
    Signed-off-by: Evan Lloyd <evan.lloyd@xxxxxxx>
    Reviewed-by: Leif Lindholm <leif.lindholm@xxxxxxxxxx>

commit 23d6348f924d27e72acdb3b5747ca26697e677e1
Author: Sami Mujawar <sami.mujawar@xxxxxxx>
Date:   Tue May 16 11:10:44 2017 +0100

    ArmPkg: Add CNTHCTL_EL2 support functions
    
    Added helper functions for reading and writing the
    CNTHCTL_EL2 register.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Sami Mujawar <sami.mujawar@xxxxxxx>
    Signed-off-by: Evan Lloyd <evan.lloyd@xxxxxxx>
    Reviewed-by: Leif Lindholm <leif.lindholm@xxxxxxxxxx>

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