Re: [Xen-devel] [PATCH 1/3] docs: specify endianess of xenstore protocol header

[Stefano Stabellini <sstabellini@xxxxxxxxxx>]

On Mon, 8 May 2017, Ian Jackson wrote:
> Juergen Gross writes ("[PATCH 1/3] docs: specify endianess of xenstore 
> protocol header"):
> > The endianess of the xenstore protocol header should be specified.
> ...
> > -followed by xsd_sockmsg.len bytes of payload.
> > +followed by xsd_sockmsg.len bytes of payload. The header fields are
> > +all in little endian byte order.
> 
> Yes, but this is not correct.  On a big-endian cpu, they would be in
> big-endian.
> 
> On a bytesexual cpu, the endianness should be specified but it will be
> the same endianness as shared ring fields, etc.  So this doc probably
> ought not to contain a list of endiannesses.  Best just to say that
> the fields are all in host native byte order.

We only have two supported architectures today: x86 and ARM. Speaking
for ARM, we need to say clearly that it's little endian, because ARM
actually support both and it is possible to have a mix of big and little
endian guests on a little endian hypervisor.

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