[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH v3 04/26] ARM: GICv3 ITS: map ITS command buffer
On Fri, 31 Mar 2017, Andre Przywara wrote: > Instead of directly manipulating the tables in memory, an ITS driver > sends commands via a ring buffer in normal system memory to the ITS h/w > to create or alter the LPI mappings. > Allocate memory for that buffer and tell the ITS about it to be able > to send ITS commands. > > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx> Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx> > --- > xen/arch/arm/gic-v3-its.c | 53 > ++++++++++++++++++++++++++++++++++++++++ > xen/include/asm-arm/gic_v3_its.h | 6 +++++ > 2 files changed, 59 insertions(+) > > diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c > index bfdb7ac..9a86769 100644 > --- a/xen/arch/arm/gic-v3-its.c > +++ b/xen/arch/arm/gic-v3-its.c > @@ -20,10 +20,13 @@ > > #include <xen/lib.h> > #include <xen/mm.h> > +#include <xen/sizes.h> > #include <asm/gic_v3_defs.h> > #include <asm/gic_v3_its.h> > #include <asm/io.h> > > +#define ITS_CMD_QUEUE_SZ SZ_1M > + > LIST_HEAD(host_its_list); > > bool gicv3_its_host_has_its(void) > @@ -56,6 +59,51 @@ static uint64_t encode_propbaser_phys_addr(paddr_t addr, > unsigned int page_bits) > return ret | ((addr & GENMASK_ULL(51, 48)) >> (48 - 12)); > } > > +static void *its_map_cbaser(struct host_its *its) > +{ > + void __iomem *cbasereg = its->its_base + GITS_CBASER; > + uint64_t reg; > + void *buffer; > + > + reg = GIC_BASER_InnerShareable << GITS_BASER_SHAREABILITY_SHIFT; > + reg |= GIC_BASER_CACHE_SameAsInner << > GITS_BASER_OUTER_CACHEABILITY_SHIFT; > + reg |= GIC_BASER_CACHE_RaWaWb << GITS_BASER_INNER_CACHEABILITY_SHIFT; > + > + buffer = _xzalloc(ITS_CMD_QUEUE_SZ, SZ_64K); > + if ( !buffer ) > + return NULL; > + > + if ( virt_to_maddr(buffer) & ~GENMASK_ULL(51, 12) ) > + { > + xfree(buffer); > + return NULL; > + } > + > + reg |= GITS_VALID_BIT | virt_to_maddr(buffer); > + reg |= ((ITS_CMD_QUEUE_SZ / SZ_4K) - 1) & GITS_CBASER_SIZE_MASK; > + writeq_relaxed(reg, cbasereg); > + reg = readq_relaxed(cbasereg); > + > + /* If the ITS dropped shareability, drop cacheability as well. */ > + if ( (reg & GITS_BASER_SHAREABILITY_MASK) == 0 ) > + { > + reg &= ~GITS_BASER_INNER_CACHEABILITY_MASK; > + writeq_relaxed(reg, cbasereg); > + } > + > + /* > + * If the command queue memory is mapped as uncached, we need to flush > + * it on every access. > + */ > + if ( !(reg & GITS_BASER_INNER_CACHEABILITY_MASK) ) > + { > + its->flags |= HOST_ITS_FLUSH_CMD_QUEUE; > + printk(XENLOG_WARNING "using non-cacheable ITS command queue\n"); > + } > + > + return buffer; > +} > + > /* The ITS BASE registers work with page sizes of 4K, 16K or 64K. */ > #define BASER_PAGE_BITS(sz) ((sz) * 2 + 12) > > @@ -179,6 +227,11 @@ static int gicv3_its_init_single_its(struct host_its > *hw_its) > } > } > > + hw_its->cmd_buf = its_map_cbaser(hw_its); > + if ( !hw_its->cmd_buf ) > + return -ENOMEM; > + writeq_relaxed(0, hw_its->its_base + GITS_CWRITER); > + > return 0; > } > > diff --git a/xen/include/asm-arm/gic_v3_its.h > b/xen/include/asm-arm/gic_v3_its.h > index badb644..f21162a 100644 > --- a/xen/include/asm-arm/gic_v3_its.h > +++ b/xen/include/asm-arm/gic_v3_its.h > @@ -74,8 +74,12 @@ > #define GITS_BASER_OUTER_CACHEABILITY_MASK (0x7ULL << > GITS_BASER_OUTER_CACHEABILITY_SHIFT) > #define GITS_BASER_INNER_CACHEABILITY_MASK (0x7ULL << > GITS_BASER_INNER_CACHEABILITY_SHIFT) > > +#define GITS_CBASER_SIZE_MASK 0xff > + > #include <xen/device_tree.h> > > +#define HOST_ITS_FLUSH_CMD_QUEUE (1U << 0) > + > /* data structure for each hardware ITS */ > struct host_its { > struct list_head entry; > @@ -84,6 +88,8 @@ struct host_its { > paddr_t size; > void __iomem *its_base; > unsigned int devid_bits; > + void *cmd_buf; > + unsigned int flags; > }; > > > -- > 2.9.0 > _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx https://lists.xen.org/xen-devel
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