Re: [Xen-devel] Question about the general performance counter overflow interrupt handling

[Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>]

>> When I program the general performance counter to trigger an overflow
>> interrupt, I set the following bits for the event selector register
>> and run a task to generate the L3 cache cache miss.
>> FLAG_ENABLE: 0x400000UL
>> FLAG_INT:    0x100000UL
>> FLAG_USR: 0x010000UL
>> L3_ALLMISS_EVENT    0x2E
>> L3_ALLMISS_MESI     0x41
>>
>> I'm sure the performance counter does overflow, but I didn't see any
>> interrupt was triggered. Maybe I missed something?

Did you program global registrers (MSR_CORE_PERF_GLOBAL_CTRL,
MSR_CORE_PERF_GLOBAL_OVF_CTRL)?

-boris


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