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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v3 1/8] x86/vioapic: expand hvm_vioapic to contain vIO APIC internal state
This is required in order to have a variable number of vIO APIC pins, instead
of the current fixed value (48). Note that this patch only expands the fields
of the hvm_vioapic struct, without actually introducing any new fields or
functionality.
The reason to expand the hvm_vioapic structure instead of the hvm_hw_vioapic
one is that the variable number of pins functionality is only going to be used
by the hardware domain, so no modifications are needed to the save format.
Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
---
Cc: Jan Beulich <jbeulich@xxxxxxxx>
Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
Changes since v2:
- Change patch title.
- Use an unnamed struct to store the vioapic state inside of hvm_vioapic.
- Use a define to declare the hvm_hw_vioapic struct (and the equivalent
unnamed struct inside of hvm_vioapic).
- Remove the BUILD_BUG_ON.
Changes since v1:
- New in this version.
---
xen/arch/x86/hvm/vioapic.c | 39 +++++++++++++------------
xen/include/asm-x86/hvm/vioapic.h | 10 ++++---
xen/include/public/arch-x86/hvm/save.h | 53 ++++++++++++++++++++--------------
3 files changed, 57 insertions(+), 45 deletions(-)
diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c
index fdbb21f097..23abdfc4c6 100644
--- a/xen/arch/x86/hvm/vioapic.c
+++ b/xen/arch/x86/hvm/vioapic.c
@@ -42,9 +42,9 @@
/* HACK: Route IRQ0 only to VCPU0 to prevent time jumps. */
#define IRQ0_SPECIAL_ROUTING 1
-static void vioapic_deliver(struct hvm_hw_vioapic *vioapic, int irq);
+static void vioapic_deliver(struct hvm_vioapic *vioapic, int irq);
-static uint32_t vioapic_read_indirect(const struct hvm_hw_vioapic *vioapic)
+static uint32_t vioapic_read_indirect(const struct hvm_vioapic *vioapic)
{
uint32_t result = 0;
@@ -94,7 +94,7 @@ static int vioapic_read(
struct vcpu *v, unsigned long addr,
unsigned int length, unsigned long *pval)
{
- const struct hvm_hw_vioapic *vioapic = domain_vioapic(v->domain);
+ const struct hvm_vioapic *vioapic = domain_vioapic(v->domain);
uint32_t result;
HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "addr %lx", addr);
@@ -119,7 +119,7 @@ static int vioapic_read(
}
static void vioapic_write_redirent(
- struct hvm_hw_vioapic *vioapic, unsigned int idx,
+ struct hvm_vioapic *vioapic, unsigned int idx,
int top_word, uint32_t val)
{
struct domain *d = vioapic_domain(vioapic);
@@ -170,7 +170,7 @@ static void vioapic_write_redirent(
}
static void vioapic_write_indirect(
- struct hvm_hw_vioapic *vioapic, uint32_t val)
+ struct hvm_vioapic *vioapic, uint32_t val)
{
switch ( vioapic->ioregsel )
{
@@ -215,7 +215,7 @@ static int vioapic_write(
struct vcpu *v, unsigned long addr,
unsigned int length, unsigned long val)
{
- struct hvm_hw_vioapic *vioapic = domain_vioapic(v->domain);
+ struct hvm_vioapic *vioapic = domain_vioapic(v->domain);
switch ( addr & 0xff )
{
@@ -242,7 +242,7 @@ static int vioapic_write(
static int vioapic_range(struct vcpu *v, unsigned long addr)
{
- struct hvm_hw_vioapic *vioapic = domain_vioapic(v->domain);
+ struct hvm_vioapic *vioapic = domain_vioapic(v->domain);
return ((addr >= vioapic->base_address &&
(addr < vioapic->base_address + VIOAPIC_MEM_LENGTH)));
@@ -255,7 +255,7 @@ static const struct hvm_mmio_ops vioapic_mmio_ops = {
};
static void ioapic_inj_irq(
- struct hvm_hw_vioapic *vioapic,
+ struct hvm_vioapic *vioapic,
struct vlapic *target,
uint8_t vector,
uint8_t trig_mode,
@@ -275,7 +275,7 @@ static inline int pit_channel0_enabled(void)
return pt_active(¤t->domain->arch.vpit.pt0);
}
-static void vioapic_deliver(struct hvm_hw_vioapic *vioapic, int irq)
+static void vioapic_deliver(struct hvm_vioapic *vioapic, int irq)
{
uint16_t dest = vioapic->redirtbl[irq].fields.dest_id;
uint8_t dest_mode = vioapic->redirtbl[irq].fields.dest_mode;
@@ -361,7 +361,7 @@ static void vioapic_deliver(struct hvm_hw_vioapic *vioapic,
int irq)
void vioapic_irq_positive_edge(struct domain *d, unsigned int irq)
{
- struct hvm_hw_vioapic *vioapic = domain_vioapic(d);
+ struct hvm_vioapic *vioapic = domain_vioapic(d);
union vioapic_redir_entry *ent;
ASSERT(has_vioapic(d));
@@ -388,7 +388,7 @@ void vioapic_irq_positive_edge(struct domain *d, unsigned
int irq)
void vioapic_update_EOI(struct domain *d, u8 vector)
{
- struct hvm_hw_vioapic *vioapic = domain_vioapic(d);
+ struct hvm_vioapic *vioapic = domain_vioapic(d);
struct hvm_irq *hvm_irq = &d->arch.hvm_domain.irq;
union vioapic_redir_entry *ent;
int gsi;
@@ -426,38 +426,39 @@ void vioapic_update_EOI(struct domain *d, u8 vector)
static int ioapic_save(struct domain *d, hvm_domain_context_t *h)
{
- struct hvm_hw_vioapic *s = domain_vioapic(d);
+ struct hvm_vioapic *s = domain_vioapic(d);
if ( !has_vioapic(d) )
return 0;
- return hvm_save_entry(IOAPIC, 0, h, s);
+ return hvm_save_entry(IOAPIC, 0, h, &s->domU);
}
static int ioapic_load(struct domain *d, hvm_domain_context_t *h)
{
- struct hvm_hw_vioapic *s = domain_vioapic(d);
+ struct hvm_vioapic *s = domain_vioapic(d);
if ( !has_vioapic(d) )
return -ENODEV;
- return hvm_load_entry(IOAPIC, h, s);
+ return hvm_load_entry(IOAPIC, h, &s->domU);
}
HVM_REGISTER_SAVE_RESTORE(IOAPIC, ioapic_save, ioapic_load, 1, HVMSR_PER_DOM);
void vioapic_reset(struct domain *d)
{
- struct hvm_vioapic *vioapic = d->arch.hvm_domain.vioapic;
+ struct hvm_vioapic *vioapic = domain_vioapic(d);
int i;
if ( !has_vioapic(d) )
return;
- memset(&vioapic->hvm_hw_vioapic, 0, sizeof(vioapic->hvm_hw_vioapic));
+ memset(vioapic, 0, sizeof(*vioapic));
+ vioapic->domain = d;
for ( i = 0; i < VIOAPIC_NUM_PINS; i++ )
- vioapic->hvm_hw_vioapic.redirtbl[i].fields.mask = 1;
- vioapic->hvm_hw_vioapic.base_address = VIOAPIC_DEFAULT_BASE_ADDRESS;
+ vioapic->redirtbl[i].fields.mask = 1;
+ vioapic->base_address = VIOAPIC_DEFAULT_BASE_ADDRESS;
}
int vioapic_init(struct domain *d)
diff --git a/xen/include/asm-x86/hvm/vioapic.h
b/xen/include/asm-x86/hvm/vioapic.h
index 745c09ab5c..ab7be9e741 100644
--- a/xen/include/asm-x86/hvm/vioapic.h
+++ b/xen/include/asm-x86/hvm/vioapic.h
@@ -48,13 +48,15 @@
#define VIOAPIC_REG_RTE0 0x10
struct hvm_vioapic {
- struct hvm_hw_vioapic hvm_hw_vioapic;
struct domain *domain;
+ union {
+ XEN_HVM_VIOAPIC(, VIOAPIC_NUM_PINS);
+ struct hvm_hw_vioapic domU;
+ };
};
-#define domain_vioapic(d) (&(d)->arch.hvm_domain.vioapic->hvm_hw_vioapic)
-#define vioapic_domain(v) (container_of((v), struct hvm_vioapic, \
- hvm_hw_vioapic)->domain)
+#define domain_vioapic(d) ((d)->arch.hvm_domain.vioapic)
+#define vioapic_domain(v) ((v)->domain)
int vioapic_init(struct domain *d);
void vioapic_deinit(struct domain *d);
diff --git a/xen/include/public/arch-x86/hvm/save.h
b/xen/include/public/arch-x86/hvm/save.h
index 66ae1a2b80..ab848f6467 100644
--- a/xen/include/public/arch-x86/hvm/save.h
+++ b/xen/include/public/arch-x86/hvm/save.h
@@ -361,30 +361,39 @@ DECLARE_HVM_SAVE_TYPE(PIC, 3, struct hvm_hw_vpic);
* IO-APIC
*/
+union vioapic_redir_entry
+{
+ uint64_t bits;
+ struct {
+ uint8_t vector;
+ uint8_t delivery_mode:3;
+ uint8_t dest_mode:1;
+ uint8_t delivery_status:1;
+ uint8_t polarity:1;
+ uint8_t remote_irr:1;
+ uint8_t trig_mode:1;
+ uint8_t mask:1;
+ uint8_t reserve:7;
+ uint8_t reserved[4];
+ uint8_t dest_id;
+ } fields;
+};
+
#define VIOAPIC_NUM_PINS 48 /* 16 ISA IRQs, 32 non-legacy PCI IRQS. */
-struct hvm_hw_vioapic {
- uint64_t base_address;
- uint32_t ioregsel;
- uint32_t id;
- union vioapic_redir_entry
- {
- uint64_t bits;
- struct {
- uint8_t vector;
- uint8_t delivery_mode:3;
- uint8_t dest_mode:1;
- uint8_t delivery_status:1;
- uint8_t polarity:1;
- uint8_t remote_irr:1;
- uint8_t trig_mode:1;
- uint8_t mask:1;
- uint8_t reserve:7;
- uint8_t reserved[4];
- uint8_t dest_id;
- } fields;
- } redirtbl[VIOAPIC_NUM_PINS];
-};
+#define XEN_HVM_VIOAPIC(name, cnt) \
+ struct name { \
+ uint64_t base_address; \
+ uint32_t ioregsel; \
+ uint32_t id; \
+ union vioapic_redir_entry redirtbl[cnt]; \
+ }
+
+XEN_HVM_VIOAPIC(hvm_hw_vioapic, VIOAPIC_NUM_PINS);
+
+#ifndef __XEN__
+#undef XEN_HVM_VIOAPIC
+#endif
DECLARE_HVM_SAVE_TYPE(IOAPIC, 4, struct hvm_hw_vioapic);
--
2.11.0 (Apple Git-81)
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