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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v2 14/27] ARM: vGICv3: introduce basic ITS emulation bits
Create a new file to hold the emulation code for the ITS widget. For now we emulate the memory mapped ITS registers and provide a stub to introduce the ITS command handling framework (but without actually emulating any commands at this time). Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx> --- xen/arch/arm/Makefile | 1 + xen/arch/arm/vgic-v3-its.c | 487 ++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic-v3.c | 9 - xen/include/asm-arm/gic_v3_defs.h | 19 ++ 4 files changed, 507 insertions(+), 9 deletions(-) create mode 100644 xen/arch/arm/vgic-v3-its.c diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 02a8737..e7ce2c83 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -47,6 +47,7 @@ obj-y += traps.o obj-y += vgic.o obj-y += vgic-v2.o obj-$(CONFIG_HAS_GICV3) += vgic-v3.o +obj-$(CONFIG_HAS_ITS) += vgic-v3-its.o obj-y += vm_event.o obj-y += vtimer.o obj-y += vpsci.o diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c new file mode 100644 index 0000000..5337638 --- /dev/null +++ b/xen/arch/arm/vgic-v3-its.c @@ -0,0 +1,487 @@ +/* + * xen/arch/arm/vgic-v3-its.c + * + * ARM Interrupt Translation Service (ITS) emulation + * + * Andre Przywara <andre.przywara@xxxxxxx> + * Copyright (c) 2016,2017 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; under version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see <http://www.gnu.org/licenses/>. + */ + +#include <xen/bitops.h> +#include <xen/config.h> +#include <xen/domain_page.h> +#include <xen/lib.h> +#include <xen/init.h> +#include <xen/softirq.h> +#include <xen/irq.h> +#include <xen/sched.h> +#include <xen/sizes.h> +#include <asm/current.h> +#include <asm/mmio.h> +#include <asm/gic_v3_defs.h> +#include <asm/gic_v3_its.h> +#include <asm/vgic.h> +#include <asm/vgic-emul.h> + +/* Data structure to describe a virtual ITS */ +struct virt_its { + struct domain *d; + spinlock_t vcmd_lock; /* protects the virtual command buffer */ + uint64_t cbaser; + uint64_t *cmdbuf; + int cwriter; + int creadr; + spinlock_t its_lock; /* protects the collection and device tables */ + uint64_t baser0, baser1; + uint16_t *coll_table; + int max_collections; + uint64_t *dev_table; + int max_devices; + bool enabled; +}; + +/* + * An Interrupt Translation Table Entry: this is indexed by a + * DeviceID/EventID pair and is located in guest memory. + */ +struct vits_itte +{ + uint32_t vlpi; + uint16_t collection; +}; + +/************************************** + * Functions that handle ITS commands * + **************************************/ + +static uint64_t its_cmd_mask_field(uint64_t *its_cmd, + int word, int shift, int size) +{ + return (le64_to_cpu(its_cmd[word]) >> shift) & (BIT(size) - 1); +} + +#define its_cmd_get_command(cmd) its_cmd_mask_field(cmd, 0, 0, 8) +#define its_cmd_get_deviceid(cmd) its_cmd_mask_field(cmd, 0, 32, 32) +#define its_cmd_get_size(cmd) its_cmd_mask_field(cmd, 1, 0, 5) +#define its_cmd_get_id(cmd) its_cmd_mask_field(cmd, 1, 0, 32) +#define its_cmd_get_physical_id(cmd) its_cmd_mask_field(cmd, 1, 32, 32) +#define its_cmd_get_collection(cmd) its_cmd_mask_field(cmd, 2, 0, 16) +#define its_cmd_get_target_addr(cmd) its_cmd_mask_field(cmd, 2, 16, 32) +#define its_cmd_get_validbit(cmd) its_cmd_mask_field(cmd, 2, 63, 1) + +#define ITS_CMD_BUFFER_SIZE(baser) ((((baser) & 0xff) + 1) << 12) + +static int vgic_its_handle_cmds(struct domain *d, struct virt_its *its, + uint32_t writer) +{ + uint64_t *cmdptr; + + if ( !its->cmdbuf ) + return -1; + + if ( writer >= ITS_CMD_BUFFER_SIZE(its->cbaser) ) + return -1; + + spin_lock(&its->vcmd_lock); + + while ( its->creadr != writer ) + { + cmdptr = its->cmdbuf + (its->creadr / sizeof(*its->cmdbuf)); + switch (its_cmd_get_command(cmdptr)) + { + case GITS_CMD_SYNC: + /* We handle ITS commands synchronously, so we ignore SYNC. */ + break; + default: + gdprintk(XENLOG_G_WARNING, "ITS: unhandled ITS command %ld\n", + its_cmd_get_command(cmdptr)); + break; + } + + its->creadr += ITS_CMD_SIZE; + if ( its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser) ) + its->creadr = 0; + } + its->cwriter = writer; + + spin_unlock(&its->vcmd_lock); + + return 0; +} + +/***************************** + * ITS registers read access * + *****************************/ + +/* + * The physical address is encoded slightly differently depending on + * the used page size: the highest four bits are stored in the lowest + * four bits of the field for 64K pages. + */ +static paddr_t get_baser_phys_addr(uint64_t reg) +{ + if ( reg & BIT(9) ) + return (reg & GENMASK(47, 16)) | ((reg & GENMASK(15, 12)) << 36); + else + return reg & GENMASK(47, 12); +} + +static int vgic_v3_its_mmio_read(struct vcpu *v, mmio_info_t *info, + register_t *r, void *priv) +{ + struct virt_its *its = priv; + + switch ( info->gpa & 0xffff ) + { + case VREG32(GITS_CTLR): + if ( info->dabt.size != DABT_WORD ) goto bad_width; + *r = vgic_reg32_extract(its->enabled | BIT(31), info); + break; + case VREG32(GITS_IIDR): + if ( info->dabt.size != DABT_WORD ) goto bad_width; + *r = vgic_reg32_extract(GITS_IIDR_VALUE, info); + break; + case VREG64(GITS_TYPER): + if ( info->dabt.size < DABT_WORD ) goto bad_width; + *r = vgic_reg64_extract(0x1eff1, info); + break; + case VREG64(GITS_CBASER): + if ( info->dabt.size < DABT_WORD ) goto bad_width; + *r = vgic_reg64_extract(its->cbaser, info); + break; + case VREG64(GITS_CWRITER): + if ( info->dabt.size < DABT_WORD ) goto bad_width; + *r = vgic_reg64_extract(its->cwriter, info); + break; + case VREG64(GITS_CREADR): + if ( info->dabt.size < DABT_WORD ) goto bad_width; + *r = vgic_reg64_extract(its->creadr, info); + break; + case VREG64(GITS_BASER0): + if ( info->dabt.size < DABT_WORD ) goto bad_width; + *r = vgic_reg64_extract(its->baser0, info); + break; + case VREG64(GITS_BASER1): + if ( info->dabt.size < DABT_WORD ) goto bad_width; + *r = vgic_reg64_extract(its->baser1, info); + break; + case VRANGE64(GITS_BASER2, GITS_BASER7): + if ( info->dabt.size < DABT_WORD ) goto bad_width; + *r = vgic_reg64_extract(0, info); + break; + case VREG32(GICD_PIDR2): + if ( info->dabt.size != DABT_WORD ) goto bad_width; + *r = vgic_reg32_extract(GICV3_GICD_PIDR2, info); + break; + } + + return 1; + +bad_width: + domain_crash_synchronous(); + + return 0; +} + +/****************************** + * ITS registers write access * + ******************************/ + +static int its_baser_table_size(uint64_t baser) +{ + int page_size = 0; + + switch ( (baser >> 8) & 3 ) + { + case 0: page_size = SZ_4K; break; + case 1: page_size = SZ_16K; break; + case 2: + case 3: page_size = SZ_64K; break; + } + + return page_size * ((baser & GENMASK(7, 0)) + 1); +} + +static int its_baser_nr_entries(uint64_t baser) +{ + int entry_size = ((baser & GENMASK(52, 48)) >> 48) + 1; + + return its_baser_table_size(baser) / entry_size; +} + +static void vgic_its_map_cmdbuf(struct virt_its *its) +{ + if ( its->cmdbuf || !(its->cbaser & GITS_VALID_BIT) ) + return; + + get_guest_pages(its->d, its->cbaser & GENMASK(51, 12), + (its->cbaser & 0xff) + 1); + its->cmdbuf = map_guest_pages(its->d, its->cbaser & GENMASK(51, 12), + (its->cbaser & 0xff) + 1); +} + +static void vgic_its_unmap_cmdbuf(struct virt_its *its) +{ + int nr_pages = (its->cbaser & 0xff) + 1; + + if ( !its->cmdbuf ) + return; + + unmap_guest_pages(its->cmdbuf, nr_pages); + put_guest_pages(its->d, its->cbaser & GENMASK(51, 12), nr_pages); + + its->cmdbuf = NULL; +} + +static void* vgic_its_map_its_table(struct virt_its *its, uint64_t reg) +{ + void *ret; + int table_size = its_baser_table_size(reg); + + if ( !(reg & GITS_VALID_BIT) ) + return NULL; + + get_guest_pages(its->d, get_baser_phys_addr(reg), table_size >> PAGE_SHIFT); + ret = map_guest_pages(its->d, get_baser_phys_addr(reg), + table_size >> PAGE_SHIFT); + memset(ret, 0, table_size); + + return ret; +} + +static void vgic_its_unmap_its_table(struct domain *d, void *table, + uint64_t reg) +{ + if ( !table ) + return; + + unmap_guest_pages(table, its_baser_table_size(reg) >> PAGE_SHIFT); + put_guest_pages(d, get_baser_phys_addr(reg), + its_baser_table_size(reg) >> PAGE_SHIFT); +} + +static void vgic_v3_its_change_its_status(struct virt_its *its, bool status) +{ + if ( !status ) + { + its->enabled = false; + return; + } + + vgic_its_map_cmdbuf(its); + + if ( !its->dev_table ) + its->dev_table = vgic_its_map_its_table(its, its->baser0); + + if ( !its->coll_table ) + its->coll_table = vgic_its_map_its_table(its, its->baser1); + + its->enabled = true; +} + +static void sanitize_its_base_reg(uint64_t *reg) +{ + uint64_t r = *reg; + + /* Avoid outer shareable. */ + switch ( (r >> GITS_BASER_SHAREABILITY_SHIFT) & 0x03 ) + { + case GIC_BASER_OuterShareable: + r = r & ~GITS_BASER_SHAREABILITY_MASK; + r |= GIC_BASER_InnerShareable << GITS_BASER_SHAREABILITY_SHIFT; + break; + default: + break; + } + + /* Avoid any inner non-cacheable mapping. */ + switch ( (r >> GITS_BASER_INNER_CACHEABILITY_SHIFT) & 0x07 ) + { + case GIC_BASER_CACHE_nCnB: + case GIC_BASER_CACHE_nC: + r = r & ~GITS_BASER_INNER_CACHEABILITY_MASK; + r |= GIC_BASER_CACHE_RaWb << GITS_BASER_INNER_CACHEABILITY_SHIFT; + break; + default: + break; + } + + /* Only allow non-cacheable or same-as-inner. */ + switch ( (r >> GITS_BASER_OUTER_CACHEABILITY_SHIFT) & 0x07 ) + { + case GIC_BASER_CACHE_SameAsInner: + case GIC_BASER_CACHE_nC: + break; + default: + r = r & ~GITS_BASER_OUTER_CACHEABILITY_MASK; + r |= GIC_BASER_CACHE_nC << GITS_BASER_OUTER_CACHEABILITY_SHIFT; + break; + } + + *reg = r; +} + +static int vgic_v3_its_mmio_write(struct vcpu *v, mmio_info_t *info, + register_t r, void *priv) +{ + struct domain *d = v->domain; + struct virt_its *its = priv; + uint64_t reg; + uint32_t reg32, ctlr; + + switch ( info->gpa & 0xffff ) + { + case VREG32(GITS_CTLR): + if ( info->dabt.size != DABT_WORD ) goto bad_width; + + ctlr = its->enabled ? GITS_CTLR_ENABLE : 0; + reg32 = ctlr; + vgic_reg32_update(®32, r, info); + its->enabled = reg32 & GITS_CTLR_ENABLE; + + if ( ctlr ^ reg32 ) + vgic_v3_its_change_its_status(its, its->enabled); + return 1; + + case VREG32(GITS_IIDR): + goto write_ignore_32; + case VREG32(GITS_TYPER): + goto write_ignore_32; + case VREG64(GITS_CBASER): + if ( info->dabt.size < DABT_WORD ) goto bad_width; + + /* Changing base registers with the ITS enabled is UNPREDICTABLE. */ + if ( its->enabled ) + return 1; + + reg = its->cbaser; + vgic_reg64_update(®, r, info); + sanitize_its_base_reg(®); + + vgic_its_unmap_cmdbuf(its); + its->cbaser = reg; + + return 1; + + case VREG64(GITS_CWRITER): + if ( info->dabt.size < DABT_WORD ) goto bad_width; + reg = its->cwriter & 0xfffe0; + vgic_reg64_update(®, r, info); + its->cwriter = reg & 0xfffe0; + + if ( its->enabled ) + vgic_its_handle_cmds(d, its, reg); + + return 1; + + case VREG64(GITS_CREADR): + goto write_ignore_64; + case VREG64(GITS_BASER0): + if ( info->dabt.size < DABT_WORD ) goto bad_width; + + /* Changing base registers with the ITS enabled is UNPREDICTABLE. */ + if ( its->enabled ) + return 1; + + reg = its->baser0; + vgic_reg64_update(®, r, info); + + reg &= ~GITS_BASER_RO_MASK; + reg |= (sizeof(uint64_t) - 1) << GITS_BASER_ENTRY_SIZE_SHIFT; + reg |= GITS_BASER_TYPE_DEVICE << GITS_BASER_TYPE_SHIFT; + sanitize_its_base_reg(®); + + /* Has the table address been changed or invalidated? */ + if ( !(reg & GITS_VALID_BIT) || + get_baser_phys_addr(reg) != get_baser_phys_addr(its->baser0) ) + { + vgic_its_unmap_its_table(its->d, its->dev_table, reg); + its->dev_table = NULL; + } + + if ( reg & GITS_VALID_BIT ) + its->max_devices = its_baser_nr_entries(reg); + else + its->max_devices = 0; + + its->baser0 = reg; + return 1; + case VREG64(GITS_BASER1): + if ( info->dabt.size < DABT_WORD ) goto bad_width; + + /* Changing base registers with the ITS enabled is UNPREDICTABLE. */ + if ( its->enabled ) + return 1; + + reg = its->baser1; + vgic_reg64_update(®, r, info); + reg &= ~GITS_BASER_RO_MASK; + reg |= (sizeof(uint16_t) - 1) << GITS_BASER_ENTRY_SIZE_SHIFT; + reg |= GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT; + sanitize_its_base_reg(®); + + if ( !(reg & GITS_VALID_BIT) || + get_baser_phys_addr(reg) != get_baser_phys_addr(its->baser1) ) + { + vgic_its_unmap_its_table(its->d, its->coll_table, reg); + its->coll_table = NULL; + } + + if ( reg & GITS_VALID_BIT ) + its->max_collections = its_baser_nr_entries(reg); + else + its->max_collections = 0; + its->baser1 = reg; + return 1; + case VRANGE64(GITS_BASER2, GITS_BASER7): + goto write_ignore_64; + default: + gdprintk(XENLOG_G_WARNING, "ITS: unhandled ITS register 0x%lx\n", + info->gpa & 0xffff); + return 0; + } + + return 1; + +write_ignore_64: + if ( ! vgic_reg64_check_access(info->dabt) ) goto bad_width; + return 1; + +write_ignore_32: + if ( info->dabt.size != DABT_WORD ) goto bad_width; + return 1; + +bad_width: + printk(XENLOG_G_ERR "%pv vGICR: bad read width %d r%d offset %#08lx\n", + v, info->dabt.size, info->dabt.reg, info->gpa & 0xffff); + + domain_crash_synchronous(); + + return 0; +} + +static const struct mmio_handler_ops vgic_its_mmio_handler = { + .read = vgic_v3_its_mmio_read, + .write = vgic_v3_its_mmio_write, +}; + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index de625bf..d1382be 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -159,15 +159,6 @@ static void vgic_store_irouter(struct domain *d, struct vgic_irq_rank *rank, rank->vcpu[offset] = new_vcpu->vcpu_id; } -static inline bool vgic_reg64_check_access(struct hsr_dabt dabt) -{ - /* - * 64 bits registers can be accessible using 32-bit and 64-bit unless - * stated otherwise (See 8.1.3 ARM IHI 0069A). - */ - return ( dabt.size == DABT_DOUBLE_WORD || dabt.size == DABT_WORD ); -} - static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, uint32_t gicr_reg, register_t *r) diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index 878bae2..1e88d6b 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -153,6 +153,16 @@ #define LPI_PROP_RES1 (1 << 1) #define LPI_PROP_ENABLED (1 << 0) +/* + * PIDR2: Only bits[7:4] are not implementation defined. We are + * emulating a GICv3 ([7:4] = 0x3). + * + * We don't emulate a specific registers scheme so implement the others + * bits as RES0 as recommended by the spec (see 8.1.13 in ARM IHI 0069A). + */ +#define GICV3_GICD_PIDR2 0x30 +#define GICV3_GICR_PIDR2 GICV3_GICD_PIDR2 + #define GICH_VMCR_EOI (1 << 9) #define GICH_VMCR_VENG1 (1 << 1) @@ -196,6 +206,15 @@ struct rdist_region { bool single_rdist; }; +/* + * 64 bits registers can be accessible using 32-bit and 64-bit unless + * stated otherwise (See 8.1.3 ARM IHI 0069A). + */ +static inline bool vgic_reg64_check_access(struct hsr_dabt dabt) +{ + return ( dabt.size == DABT_DOUBLE_WORD || dabt.size == DABT_WORD ); +} + #endif /* __ASM_ARM_GIC_V3_DEFS_H__ */ /* -- 2.9.0 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx https://lists.xen.org/xen-devel
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