[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH 0/7] Fixes to pagetable handling
On 01/03/17 16:24, Jan Beulich wrote: >>>> On 27.02.17 at 15:03, <andrew.cooper3@xxxxxxxxxx> wrote: >> Outstanding hardware issues discovered include: >> 1) There is an observable delay in AMD Fam 10h processors between loading a >> segment selector, and the results of the LDT/GDT memory access being >> visible in the pagetables (via the Access bits being set). > Are you saying the processor continues executing instructions > while the accessed bits are still clear? Or just that it takes very > long to complete the instruction doing the descriptor table access? The processor does continue to execute instructions before the access bit gets set. I discovered this because my XTF test which checks for the correct behaviour of the A/D bits tripped over it. (On that note, I really need to clean up that test and post it.) Even a 1000-nop loop isn't always enough of a delay to observe the access bit becoming set. OTOH, a serialising instruction, or forcing a memory access through the newly-loaded segment reliably cause the effects of the load to become visible. The memory access definitely occurs at the point of the implicit load, because #GP are raised properly for bad segment descriptor settings... ~Andrew _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx https://lists.xen.org/xen-devel
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