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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH v2 3/3] x86/emul: Support CPUID faulting via a speculative MSR read
>>> On 20.02.17 at 12:04, <andrew.cooper3@xxxxxxxxxx> wrote:
> On 20/02/17 10:59, Jan Beulich wrote:
>>>>> On 20.02.17 at 11:28, <andrew.cooper3@xxxxxxxxxx> wrote:
>>> --- a/xen/arch/x86/x86_emulate/x86_emulate.c
>>> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c
>>> @@ -5424,10 +5424,25 @@ x86_emulate(
>>> break;
>>>
>>> case X86EMUL_OPC(0x0f, 0xa2): /* cpuid */
>>> + msr_val = 0;
>>> fail_if(ops->cpuid == NULL);
>>> +
>>> + /* Speculatively read MSR_INTEL_MISC_FEATURES_ENABLES. */
>>> + if ( ops->read_msr &&
>>> + (rc = ops->read_msr(MSR_INTEL_MISC_FEATURES_ENABLES,
>>> + &msr_val, ctxt)) == X86EMUL_EXCEPTION )
>>> + {
>>> + /* Not implemented. Squash the exception and proceed
>>> normally. */
>>> + x86_emul_reset_event(ctxt);
>>> + rc = X86EMUL_OKAY;
>>> + }
>>> + if ( rc != X86EMUL_OKAY )
>>> + goto done;
>>> +
>>> + generate_exception_if((msr_val & MSR_MISC_FEATURES_CPUID_FAULTING)
>>> &&
>>> + !mode_ring0(), EXC_GP, 0); /* Faulting
>>> active? */
>> Could you please move the mode_ring0() check up to bypass the
>> MSR read in the first place?
>
> Ok.
With that
Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
Jan
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