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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 2/4] x86/setup: Minor cleanup to host SYSCALL MSR handling
Xen's choice of the MSR_STAR value is constant across all pcpus. Introduce a
new define and use it to avoid the opencoding in subarch_percpu_traps_init()
and restore_rest_processor_state().
Despite Intel hardware having an MSR_CSTAR register, nothing actually uses it
as the SYSCALL instruction raises #UD out of 64bit mode, meaning that
MSR_LSTAR is the only %rip value hardware will use.
Therefore, only create a CSTAR trampoline stub, and save/restore the CSTAR
value across suspend/resume on AMD hardware. MSR_CSTAR should now be
consistently 0 on Intel hardware.
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
CC: Jan Beulich <JBeulich@xxxxxxxx>
---
xen/arch/x86/acpi/suspend.c | 14 ++++++++++----
xen/arch/x86/x86_64/traps.c | 17 ++++++++++-------
xen/include/asm-x86/processor.h | 3 +++
3 files changed, 23 insertions(+), 11 deletions(-)
diff --git a/xen/arch/x86/acpi/suspend.c b/xen/arch/x86/acpi/suspend.c
index d5c67ee..37fde7d 100644
--- a/xen/arch/x86/acpi/suspend.c
+++ b/xen/arch/x86/acpi/suspend.c
@@ -32,8 +32,11 @@ void save_rest_processor_state(void)
saved_fs_base = rdfsbase();
saved_gs_base = rdgsbase();
rdmsrl(MSR_SHADOW_GS_BASE, saved_kernel_gs_base);
- rdmsrl(MSR_CSTAR, saved_cstar);
rdmsrl(MSR_LSTAR, saved_lstar);
+
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+ rdmsrl(MSR_CSTAR, saved_cstar);
+
if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR )
{
@@ -53,9 +56,12 @@ void restore_rest_processor_state(void)
/* Recover syscall MSRs */
wrmsrl(MSR_LSTAR, saved_lstar);
- wrmsrl(MSR_CSTAR, saved_cstar);
- wrmsr(MSR_STAR, 0, (FLAT_RING3_CS32<<16) | __HYPERVISOR_CS);
- wrmsr(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK, 0U);
+
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+ wrmsrl(MSR_CSTAR, saved_cstar);
+
+ wrmsrl(MSR_STAR, XEN_MSR_STAR);
+ wrmsrl(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK);
wrfsbase(saved_fs_base);
wrgsbase(saved_gs_base);
diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c
index fc8cde6..5afe286 100644
--- a/xen/arch/x86/x86_64/traps.c
+++ b/xen/arch/x86/x86_64/traps.c
@@ -403,11 +403,14 @@ void subarch_percpu_traps_init(void)
wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
}
- /* Trampoline for SYSCALL entry from compatibility mode. */
- wrmsrl(MSR_CSTAR, stub_va);
- offset += write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
- stub_va, stack_bottom,
- (unsigned long)cstar_enter);
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+ {
+ /* Trampoline for SYSCALL entry from compatibility mode. */
+ wrmsrl(MSR_CSTAR, stub_va);
+ offset += write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
+ stub_va, stack_bottom,
+ (unsigned long)cstar_enter);
+ }
/* Don't consume more than half of the stub space here. */
ASSERT(offset <= STUB_BUF_SIZE / 2);
@@ -415,8 +418,8 @@ void subarch_percpu_traps_init(void)
unmap_domain_page(stub_page);
/* Common SYSCALL parameters. */
- wrmsr(MSR_STAR, 0, ((unsigned int)FLAT_RING3_CS32 << 16) |
__HYPERVISOR_CS);
- wrmsr(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK, 0U);
+ wrmsrl(MSR_STAR, XEN_MSR_STAR);
+ wrmsrl(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK);
}
void init_int80_direct_trap(struct vcpu *v)
diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h
index 7735bc2..843f072 100644
--- a/xen/include/asm-x86/processor.h
+++ b/xen/include/asm-x86/processor.h
@@ -87,6 +87,9 @@
#define XEN_CR4_PV32_BITS (X86_CR4_SMEP|X86_CR4_SMAP)
+/* Common SYSCALL parameters. */
+#define XEN_MSR_STAR (((uint64_t)FLAT_RING3_CS32 << 48) | \
+ ((uint64_t)__HYPERVISOR_CS << 32))
#define XEN_SYSCALL_MASK (X86_EFLAGS_AC|X86_EFLAGS_VM|X86_EFLAGS_RF| \
X86_EFLAGS_NT|X86_EFLAGS_DF|X86_EFLAGS_IF| \
X86_EFLAGS_TF)
--
2.1.4
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