Re: [Xen-devel] [PATCH 4/8] x86emul: support BMI2 insns

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 13.01.17 at 19:20, <andrew.cooper3@xxxxxxxxxx> wrote:
> On 13/01/17 15:32, Jan Beulich wrote:
>> Note that the adjustment to the mode_64bit() definition is so that we
>> can avoid "#ifdef __x86_64__" around the 64-bit asm() portions. An
>> alternative would be single asm()s with a conditional branch over the
>> (manually encoded) REX64 prefix.
> 
> This presumably relying on sensible dead-code-elimitation to compile? 

Yes.

> Does this offer any further opportunities with removing other ifdefs?

When I had written this, it looked like it might, but I didn't create
any follow-up patches so far.

>> @@ -5973,6 +5987,33 @@ x86_emulate(
>>          break;
>>      }
>>  
>> +    case X86EMUL_OPC_VEX_F2(0x0f38, 0xf6): /* mulx r/m,r,r */
>> +        vcpu_must_have(bmi2);
>> +        generate_exception_if(vex.l, EXC_UD);
> 
> vex.w again.

Nope (see also the textual description, which actually mentions
VEX.L).

>> +        ea.reg = decode_register(~vex.reg & (mode_64bit() ? 0xf : 7),
>> +                                 &_regs, 0);
>> +        if ( mode_64bit() && vex.w )
>> +            asm ( "mulq %3" : "=a" (*ea.reg), "=d" (dst.val)
>> +                            : "0" (src.val), "rm" (_regs.r(dx)) );
>> +        else
>> +            asm ( "mull %3" : "=a" (*ea.reg), "=d" (dst.val)
>> +                            : "0" ((uint32_t)src.val), "rm" (_regs._edx) );
>> +        break;
>> +
>> +    case X86EMUL_OPC_VEX_F2(0x0f3a, 0xf0): /* rorx imm,r/m,r */
>> +        vcpu_must_have(bmi2);
>> +        generate_exception_if(vex.l || vex.reg != 0xf, EXC_UD);
> 
> What does this vex.reg check correspond to?  I can't locate anything
> relevant in the manuals.

Indeed the manual says nothing, but this again appears to be a
doc error: The instruction does #UD in that case. I'll add a word
to the commit message.

Jan


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