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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [RFC 04/16] x86: implement data structure of MBA.
This patch implements main data structures of MBA.
Like CAT features, MBA HW info has cos_max which means the max cos
registers number, and thrtl_max which means the max throttle value
(delay value). It also have a flag to represent if the throttle
value is linear or not.
One COS register of MBA stores a throttle value for one or more
domains. That means the transaction time between L2 cache and next
level memory will be delayed.
Signed-off-by: Yi Sun <yi.y.sun@xxxxxxxxxxxxxxx>
---
xen/arch/x86/psr.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 2c69cc0..58d3555 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -27,17 +27,23 @@
* - CDP Code and Data Prioritization
* - COS/CLOS Class of Service. Also mean COS registers.
* - COS_MAX Max number of COS for the feature (minus 1)
+ * - MBA Memory Bandwidth Allocation
* - MSRs Machine Specific Registers
* - PSR Intel Platform Shared Resource
+ * - THRTL_MAX Max throttle value (delay value) of MBA
*/
#define PSR_CMT (1<<0)
#define PSR_CAT (1<<1)
#define PSR_CDP (1<<2)
+#define PSR_MBA (1<<3)
#define CAT_CBM_LEN_MASK 0x1f
#define CAT_COS_MAX_MASK 0xffff
+/* Linear bit. */
+#define MBA_LINEAR (1<<2)
+
/*
* Per SDM 17.17.3.3 'Cache Allocation Technology: Cache Mask Configuration',
* the MSRs range from 0C90H through 0D0FH (inclusive), enables support for
@@ -79,6 +85,14 @@ enum psr_feat_type {
PSR_SOCKET_L3_CAT = 0,
PSR_SOCKET_L3_CDP,
PSR_SOCKET_L2_CAT,
+ PSR_SOCKET_MBA = 16,
+};
+
+/* MBA HW info data structure. */
+struct psr_mba_hw_info {
+ unsigned int thrtl_max;
+ unsigned int cos_max;
+ unsigned int linear;
};
/* CAT/CDP HW info data structure. */
@@ -93,6 +107,7 @@ struct feat_hw_info {
struct psr_cat_hw_info l3_cat_info;
struct psr_cat_hw_info l3_cdp_info;
struct psr_cat_hw_info l2_cat_info;
+ struct psr_mba_hw_info mba_info;
};
};
--
1.9.1
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