Re: [Xen-devel] [RFC PATCH 04/24] ARM: GICv3 ITS: map ITS command buffer

[Vijay Kilari <vijay.kilari@xxxxxxxxx>]

On Wed, Sep 28, 2016 at 11:54 PM, Andre Przywara <andre.przywara@xxxxxxx> wrote:
> Instead of directly manipulating the tables in memory, an ITS driver
> sends commands via a ring buffer to the ITS h/w to create or alter the
> LPI mappings.
> Allocate memory for that buffer and tell the ITS about it to be able
> to send ITS commands.
>
> Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
> ---
>  xen/arch/arm/gic-its.c        | 25 +++++++++++++++++++++++++
>  xen/include/asm-arm/gic-its.h |  1 +
>  2 files changed, 26 insertions(+)
>
> diff --git a/xen/arch/arm/gic-its.c b/xen/arch/arm/gic-its.c
> index 40238a2..c8a7a7e 100644
> --- a/xen/arch/arm/gic-its.c
> +++ b/xen/arch/arm/gic-its.c
> @@ -18,6 +18,7 @@
>
>  #include <xen/config.h>
>  #include <xen/lib.h>
> +#include <xen/err.h>
>  #include <xen/device_tree.h>
>  #include <xen/libfdt/libfdt.h>
>  #include <asm/p2m.h>
> @@ -56,6 +57,26 @@ static uint64_t encode_phys_addr(paddr_t addr, int 
> page_bits)
>      return ret | (addr & GENMASK(51, 48)) >> (48 - 12);
>  }
>
> +static void *gicv3_map_cbaser(void __iomem *cbasereg)
> +{
> +    uint64_t attr, reg;
> +    void *buffer;
> +
> +    attr  = GIC_BASER_InnerShareable << GITS_BASER_SHAREABILITY_SHIFT;
> +    attr |= GIC_BASER_CACHE_SameAsInner << 
> GITS_BASER_OUTER_CACHEABILITY_SHIFT;
> +    attr |= GIC_BASER_CACHE_RaWaWb << GITS_BASER_INNER_CACHEABILITY_SHIFT;
> +
> +    buffer = alloc_xenheap_pages(0, 0);
> +    if ( !buffer )
> +        return ERR_PTR(-ENOMEM);
> +
> +    /* We use exactly one 4K page, so the "Size" field is 0. */
> +    reg = attr | BIT(63) | (virt_to_maddr(buffer) & GENMASK(51, 12));

Isn't GENMASK(47, 12)?. Am I referring to wrong spec?

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