Re: [Xen-devel] [PATCH v2] x86/PV: don't wrongly hide/expose CPUID.OSXSAVE from/to user mode

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

On 19/08/16 13:53, Jan Beulich wrote:
> User mode code generally cannot be expected to invoke the PV-enabled
> CPUID Xen supports, and prior to the CPUID levelling changes for 4.7
> (as well as even nowadays on levelling incapable hardware) such CPUID
> invocations actually saw the host CR4.OSXSAVE value, whereas prior to
> this patch
> - on Intel guest user mode always saw the flag clear,
> - on AMD guest user mode saw the flag set even when the guest kernel
>   didn't enable use of XSAVE/XRSTOR.
> Fold in the guest view of CR4.OSXSAVE when setting the levelling MSRs,
> just like we do in other CPUID handling.
>
> To make guest CR4 changes immediately visible via CPUID, also invoke
> ctxt_switch_levelling() from the CR4 write path.
>
> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

I have just rerun a more thorough test, and I clearly got some incorrect
conclusions to start with.

(XEN) '1' pressed -> Extreme debugging in progress...
(XEN) Testing OSXSAVE
(XEN) ** CR4[-], MSR[-], cpuid 0
(XEN) ** CR4[+], MSR[-], cpuid 0
(XEN) ** CR4[-], MSR[+], cpuid 0
(XEN) ** CR4[+], MSR[+], cpuid 1
(XEN) '2' pressed -> Extreme debugging in progress...
(XEN) Testing APIC
(XEN) ** APIC[-], MSR[-], cpuid 0
(XEN) ** APIC[+], MSR[-], cpuid 0
(XEN) ** APIC[-], MSR[+], cpuid 0
(XEN) ** APIC[+], MSR[+], cpuid 1
(XEN) Watchdog timer detects that CPU21 is stuck!
... (an IPI hitting this core while the APIC is hard disabled appears to
get ignored, and other cores get unhappy)

So on this Sandy Bridge box does match your observation of behaviour,
and that masks are applied after fast-forwarded state.  I am rerunning
on other hardware to see how they behave.

~Andrew

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