[Xen-devel] [PATCH 2/2] x86/vmx: conditionally disable LBR support due to TSX format quirk

[Matt Wilson <msw@xxxxxxxx>]

From: Matt Wilson <msw@xxxxxxxxxx>

Systems that support LBR formats that include TSX information but do
not support TSX require special handling when saving and restoring MSR
values. For example, see the Linux kernel quirks[1, 2] in the MSR
context switching code. As a wrmsr with certain values under these
conditions causes a #GP, VM entry will fail due to MSR loading (see
last bullet of SDM 26.4 "Loading MSRS").

This failure can be triggered on a Haswell-EP system with the
following test Linux kernel module:

In domU:
  $ cat > lbr.c << EOF

  static int __init
  lbr_init(void)
  {
          u64 val;

          rdmsrl(MSR_IA32_DEBUGCTLMSR, val);
          val |= DEBUGCTLMSR_LBR;
          wrmsrl(MSR_IA32_DEBUGCTLMSR, val);

          return 0;
  }

  static void __exit
  lbr_cleanup(void)
  {
  }

  module_init(lbr_init);
  module_exit(lbr_cleanup);

  MODULE_DESCRIPTION("lbr test");
  MODULE_LICENSE("GPL");
  EOF
  $ echo "obj-m += lbr.o" > Makefile
  $ make -C /lib/modules/`uname -r`/build M=`pwd` modules
  make: Entering directory `/home/ec2-user/linux'
    CC [M]  /home/ec2-user/lbr.o
    Building modules, stage 2.
    MODPOST 1 modules
    CC      /home/ec2-user/lbr.mod.o
    LD [M]  /home/ec2-user/lbr.ko
  make: Leaving directory `/home/ec2-user/linux'
  $ sudo insmod lbr.ko
  $ Timeout, server not responding.

In dom0:
  [...]
  (XEN) Failed vm entry (exit reason 0x80000022) caused by MSR entry 1 loading.
  [...]
  (XEN) EXIT MSR load count = 0x0001
  (XEN) EXIT MSR store count = 0x0023
  (XEN) ENTRY MSR load count = 0x0023
  (XEN)   msr_count = 35
  (XEN)   msr_area[0].index=0x000001dd .data=0x1fffffff811911db
  ...

This change dynamically disables LBR save/load on systems in the
problematic configuration.

[1] 
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=71adae99ed18
[2] 
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=19fc9ddd61e0

Signed-off-by: Matt Wilson <msw@xxxxxxxxxx>
---
 xen/arch/x86/hvm/vmx/vmx.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 3d330b6..c51cefc 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2576,8 +2576,22 @@ static const struct lbr_info *last_branch_msr_get(void)
         /* Haswell */
         case 60: case 63: case 69: case 70:
         /* Broadwell */
-        case 61: case 71: case 79: case 86:
+        case 61: case 71: case 79: case 86: {
+            u64 caps;
+            bool_t tsx_support = boot_cpu_has(X86_FEATURE_HLE) ||
+                                 boot_cpu_has(X86_FEATURE_RTM);
+
+            rdmsrl(MSR_IA32_PERF_CAPABILITIES, caps);
+            /*
+             * Unimplemented fixups are required if the processor
+             * supports an LBR format that includes TSX information,
+             * but not TSX. Disable LBR save/load on such platforms.
+             */
+            if ( !tsx_support && (caps & 4) )
+                return NULL;
+
             return nh_lbr;
+        }
         /* Skylake */
         case 78: case 94:
         /* future */
-- 
1.9.1


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